From 287ce5f1ee8c3765d05bfbc0a6dd5ea9ec8b5c87 Mon Sep 17 00:00:00 2001 From: Michał Żygowski Date: Sun, 1 Dec 2019 17:41:23 +0100 Subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TEST=boot PC Engines apu1 and apu2 and launch Debian Linux Signed-off-by: Michał Żygowski Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37400 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/southbridge/amd/pi/hudson/early_setup.c | 26 +++++++++++++------------- src/southbridge/amd/pi/hudson/imc.c | 25 +++++++++++++------------ src/southbridge/amd/pi/hudson/smbus_spd.c | 10 ++-------- 3 files changed, 28 insertions(+), 33 deletions(-) (limited to 'src/southbridge/amd/pi/hudson') diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 191a96c7d4..fe75115233 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -18,6 +18,7 @@ #include #include +#include #include #include #include @@ -36,18 +37,17 @@ void configure_hudson_uart(void) { u8 byte; - byte = read8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + - CONFIG_UART_FOR_CONSOLE * sizeof(u16))); - byte |= 1 << 3; - write8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + - CONFIG_UART_FOR_CONSOLE * sizeof(u16)), byte); - byte = read8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62)); + byte = aoac_read8(FCH_AOAC_REG56 + + CONFIG_UART_FOR_CONSOLE * sizeof(u16))); byte |= 1 << 3; - write8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62), byte); - write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0); - write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0); - write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0); - write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0); + aoac_write8(FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * sizeof(u16)), + byte); + + aoac_write8(FCH_AOAC_REG62, aoac_read8(FCH_AOAC_REG62) | (1 << 3)); + iomux_write8(0x89, 0); /* UART0_RTS_L_EGPIO137 */ + iomux_write8(0x8a, 0); /* UART0_TXD_EGPIO138 */ + iomux_write8(0x8e, 0); /* UART1_RTS_L_EGPIO142 */ + iomux_write8(0x8f, 0); /* UART1_TXD_EGPIO143 */ udelay(2000); write8((void *)(0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88), @@ -229,11 +229,11 @@ void hudson_clk_output_48Mhz(void) * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so * 48Mhz will be on ball AP13 (FT3b package) */ - ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40)); + ctrl = misc_read32(FCH_MISC_REG40); /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ ctrl &= (u32)~(1<<2); - write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl); + misc_write32(FCH_MISC_REG40, ctrl); } static uintptr_t hudson_spibase(void) diff --git a/src/southbridge/amd/pi/hudson/imc.c b/src/southbridge/amd/pi/hudson/imc.c index 6a01a764cb..3c6054d147 100644 --- a/src/southbridge/amd/pi/hudson/imc.c +++ b/src/southbridge/amd/pi/hudson/imc.c @@ -16,6 +16,7 @@ #define __SIMPLE_DEVICE__ #include "imc.h" +#include #include #include #include @@ -26,24 +27,24 @@ #include #include -#define VACPI_MMIO_VBASE ((u8 *)ACPI_MMIO_BASE) - void imc_reg_init(void) { u8 reg8; /* Init Power Management Block 2 (PM2) Registers. * Check BKDG for AMD Family 16h for details. */ - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x00), 0x06); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x01), 0x06); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x02), 0xf7); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x03), 0xff); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x04), 0xff); + /* Init Power Management Block 2 (PM2) Registers. + * Check BKDG for AMD Family 16h for details. */ + pm2_write8(0, 0x06); + pm2_write8(1, 0x06); + pm2_write8(2, 0xf7); + pm2_write8(3, 0xff); + pm2_write8(4, 0xff); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x10), 0x06); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x11), 0x06); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x12), 0xf7); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x13), 0xff); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x14), 0xff); + pm2_write8(0x10, 0x06); + pm2_write8(0x11, 0x06); + pm2_write8(0x12, 0xf7); + pm2_write8(0x13, 0xff); + pm2_write8(0x14, 0xff); reg8 = pci_read_config8(PCI_DEV(0, 0x18, 0x3), 0x1E4); reg8 &= 0x8F; diff --git a/src/southbridge/amd/pi/hudson/smbus_spd.c b/src/southbridge/amd/pi/hudson/smbus_spd.c index c49ccffc4d..8523db5054 100644 --- a/src/southbridge/amd/pi/hudson/smbus_spd.c +++ b/src/southbridge/amd/pi/hudson/smbus_spd.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -127,16 +128,9 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) return 0; } -static void writePmReg (int reg, int data) -{ - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); -} - static void setupFch (int ioBase) { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); + pm_write16(0x2c, ioBase | 1); __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz } -- cgit v1.2.3