From cd49cce7b70e80b4acc49b56bb2bb94370b4d867 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 5 Mar 2019 16:53:33 -0800 Subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/amd/pi/hudson/gpio.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge/amd/pi/hudson/gpio.h') diff --git a/src/southbridge/amd/pi/hudson/gpio.h b/src/southbridge/amd/pi/hudson/gpio.h index dad2279e6c..f07855d765 100644 --- a/src/southbridge/amd/pi/hudson/gpio.h +++ b/src/southbridge/amd/pi/hudson/gpio.h @@ -25,7 +25,7 @@ #define GPIO_OUTPUT_VALUE (1 << 22) #define GPIO_OUTPUT_ENABLE (1 << 23) -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) +#if CONFIG(SOUTHBRIDGE_AMD_PI_KERN) /* GPIO_0 - GPIO_62 */ #define GPIO_BANK0_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1500) #define GPIO_0 (GPIO_BANK0_CONTROL + 0x00) @@ -124,7 +124,7 @@ #define GPIO_146 (GPIO_BANK2_CONTROL + 0x48) #define GPIO_147 (GPIO_BANK2_CONTROL + 0x4C) #define GPIO_148 (GPIO_BANK2_CONTROL + 0x50) -#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) */ +#endif /* CONFIG(SOUTHBRIDGE_AMD_PI_KERN) */ typedef uint32_t gpio_t; -- cgit v1.2.3