From c02b4fc9db3c3c1e263027382697b566127f66bb Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 22 Mar 2010 11:42:32 +0000 Subject: printk_foo -> printk(BIOS_FOO, ...) Signed-off-by: Stefan Reinauer Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/cs5536/cs5536.c | 22 +++++++++++----------- src/southbridge/amd/cs5536/cs5536_early_smbus.c | 4 ++-- src/southbridge/amd/cs5536/cs5536_ide.c | 4 ++-- src/southbridge/amd/cs5536/cs5536_smbus2.h | 8 ++++---- 4 files changed, 19 insertions(+), 19 deletions(-) (limited to 'src/southbridge/amd/cs5536') diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index e974d399d1..f068006f75 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -155,10 +155,10 @@ static void ChipsetFlashSetup(void) int i; int numEnabled = 0; - printk_debug("ChipsetFlashSetup: Start\n"); + printk(BIOS_DEBUG, "ChipsetFlashSetup: Start\n"); for (i = 0; i < FlashInitTableLen; i++) { if (FlashInitTable[i].fType != FLASH_TYPE_NONE) { - printk_debug("Enable CS%d\n", i); + printk(BIOS_DEBUG, "Enable CS%d\n", i); /* we need to configure the memory/IO mask */ msr = rdmsr(FlashPort[i]); msr.hi = 0; /* start with the "enabled" bit clear */ @@ -171,14 +171,14 @@ static void ChipsetFlashSetup(void) else msr.hi &= ~0x00000004; msr.hi |= FlashInitTable[i].fMask; - printk_debug("MSR(0x%08X, %08X_%08X)\n", FlashPort[i], + printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo); wrmsr(FlashPort[i], msr); /* now write-enable the device */ msr = rdmsr(MDD_NORF_CNTRL); msr.lo |= (1 << i); - printk_debug("MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, + printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo); wrmsr(MDD_NORF_CNTRL, msr); @@ -187,7 +187,7 @@ static void ChipsetFlashSetup(void) } } - printk_debug("ChipsetFlashSetup: Finish\n"); + printk(BIOS_DEBUG, "ChipsetFlashSetup: Finish\n"); } @@ -566,7 +566,7 @@ void chipsetinit(void) } /* Flash BAR size Setup */ - printk_err("%sDoing ChipsetFlashSetup()\n", + printk(BIOS_ERR, "%sDoing ChipsetFlashSetup()\n", sb->enable_ide_nand_flash == 1 ? "" : "Not "); if (sb->enable_ide_nand_flash == 1) ChipsetFlashSetup(); @@ -594,7 +594,7 @@ static void southbridge_init(struct device *dev) * unsigned short gpiobase = MDD_GPIO; */ - printk_err("cs5536: %s\n", __func__); + printk(BIOS_ERR, "cs5536: %s\n", __func__); setup_i8259(); lpc_init(sb); uarts_init(sb); @@ -606,7 +606,7 @@ static void southbridge_init(struct device *dev) (sb->enable_gpio_int_route >> 16)); } - printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __func__, + printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n", __func__, sb->enable_ide_nand_flash); if (sb->enable_ide_nand_flash == 1) { enable_ide_nand_flash_header(); @@ -616,7 +616,7 @@ static void southbridge_init(struct device *dev) /* disable unwanted virtual PCI devices */ for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) { - printk_debug("Disabling VPCI device: 0x%08X\n", + printk(BIOS_DEBUG, "Disabling VPCI device: 0x%08X\n", sb->unwanted_vpci[i]); outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8); outl(0xDEADBEEF, 0xCFC); @@ -644,13 +644,13 @@ static void cs5536_read_resources(device_t dev) static void southbridge_enable(struct device *dev) { - printk_err("cs5536: %s: dev is %p\n", __func__, dev); + printk(BIOS_ERR, "cs5536: %s: dev is %p\n", __func__, dev); } static void cs5536_pci_dev_enable_resources(device_t dev) { - printk_err("cs5536: %s()\n", __func__); + printk(BIOS_ERR, "cs5536: %s()\n", __func__); pci_dev_enable_resources(dev); enable_childrens_resources(dev); } diff --git a/src/southbridge/amd/cs5536/cs5536_early_smbus.c b/src/southbridge/amd/cs5536/cs5536_early_smbus.c index e5a133e903..298feeed9b 100644 --- a/src/southbridge/amd/cs5536/cs5536_early_smbus.c +++ b/src/southbridge/amd/cs5536/cs5536_early_smbus.c @@ -53,7 +53,7 @@ static int smbus_wait(unsigned smbus_io_base) if ((val & SMB_STS_SDAST) != 0) break; if (val & (SMB_STS_BER | SMB_STS_NEGACK)) { - /*printk_debug("SMBUS WAIT ERROR %x\n", val); */ + /*printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val); */ return SMBUS_ERROR; } } while (--loops); @@ -123,7 +123,7 @@ static int smbus_send_slave_address(unsigned smbus_io_base, /* check for bus conflict and NACK */ val = inb(smbus_io_base + SMB_STS); if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) { - /* printk_debug("SEND SLAVE ERROR (%x)\n", val); */ + /* printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val); */ return SMBUS_ERROR; } return smbus_wait(smbus_io_base); diff --git a/src/southbridge/amd/cs5536/cs5536_ide.c b/src/southbridge/amd/cs5536/cs5536_ide.c index bbb6bb5bcd..4acf3ed61a 100644 --- a/src/southbridge/amd/cs5536/cs5536_ide.c +++ b/src/southbridge/amd/cs5536/cs5536_ide.c @@ -36,7 +36,7 @@ static void ide_init(struct device *dev) { uint32_t ide_cfg; - printk_spew("cs5536_ide: %s\n", __func__); + printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__); /* GPIO and IRQ setup are handled in the main chipset code. */ // Enable the channel and Post Write Buffer @@ -49,7 +49,7 @@ static void ide_init(struct device *dev) static void ide_enable(struct device *dev) { - printk_spew("cs5536_ide: %s\n", __func__); + printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__); } diff --git a/src/southbridge/amd/cs5536/cs5536_smbus2.h b/src/southbridge/amd/cs5536/cs5536_smbus2.h index 3b9e96c485..a470b3714c 100644 --- a/src/southbridge/amd/cs5536/cs5536_smbus2.h +++ b/src/southbridge/amd/cs5536/cs5536_smbus2.h @@ -78,7 +78,7 @@ static int smbus_wait(unsigned smbus_io_base) if ((val & SMB_STS_SDAST) != 0) break; if (val & (SMB_STS_BER | SMB_STS_NEGACK)) { - printk_debug("SMBUS WAIT ERROR %x\n", val); + printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val); return SMBUS_ERROR; } } while (--loops); @@ -171,7 +171,7 @@ static int smbus_send_slave_address(unsigned smbus_io_base, /* check for bus conflict and NACK */ val = inb(smbus_io_base + SMB_STS); if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) { - printk_debug("SEND SLAVE ERROR (%x)\n", val); + printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val); return SMBUS_ERROR; } return smbus_wait(smbus_io_base); @@ -250,7 +250,7 @@ static void _doread(unsigned smbus_io_base, unsigned char device, return; err: - printk_debug("SMBUS READ ERROR (%d): %d\n", index, ret); + printk(BIOS_DEBUG, "SMBUS READ ERROR (%d): %d\n", index, ret); } static unsigned char do_smbus_read_byte(unsigned smbus_io_base, @@ -300,7 +300,7 @@ static int _dowrite(unsigned smbus_io_base, unsigned char device, return 0; err: - printk_debug("SMBUS WRITE ERROR: %d\n", ret); + printk(BIOS_DEBUG, "SMBUS WRITE ERROR: %d\n", ret); return -1; } -- cgit v1.2.3