From ba09695b58f7254d646618d1207840e33ca3d1d8 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Thu, 22 Apr 2010 09:22:15 +0000 Subject: fix compilation remaining geode boards Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/cs5536/chip.h | 1 - src/southbridge/amd/cs5536/cs5536.c | 26 +++++++++++++++----------- 2 files changed, 15 insertions(+), 12 deletions(-) (limited to 'src/southbridge/amd/cs5536') diff --git a/src/southbridge/amd/cs5536/chip.h b/src/southbridge/amd/cs5536/chip.h index 7d9db4e3b3..ad9e736dec 100644 --- a/src/southbridge/amd/cs5536/chip.h +++ b/src/southbridge/amd/cs5536/chip.h @@ -40,7 +40,6 @@ struct southbridge_amd_cs5536_config { unsigned int com2_address; /* e.g. 0x2F8 */ unsigned int com2_irq; /* e.g. 3 */ unsigned int unwanted_vpci[MAX_UNWANTED_VPCI]; /* the following allow you to disable unwanted virtualized PCI devices */ - }; #endif /* _SOUTHBRIDGE_AMD_CS5536 */ diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 2a3662c517..f5de337bbe 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -40,7 +40,7 @@ struct msrinit { }; /* Master Configuration Register for Bus Masters.*/ -struct msrinit SB_MASTER_CONF_TABLE[] = { +static struct msrinit SB_MASTER_CONF_TABLE[] = { {USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}}, {ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000}}, {AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}}, @@ -49,7 +49,7 @@ struct msrinit SB_MASTER_CONF_TABLE[] = { }; /* 5536 Clock Gating*/ -struct msrinit CS5536_CLOCK_GATING_TABLE[] = { +static struct msrinit CS5536_CLOCK_GATING_TABLE[] = { /* MSR Setting*/ {GLIU_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}}, {GLPCI_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}}, @@ -65,7 +65,7 @@ struct acpiinit { u32 regdata; }; -struct acpiinit acpi_init_table[] = { +static struct acpiinit acpi_init_table[] = { {ACPI_IO_BASE + 0x00, 0x01000000}, {ACPI_IO_BASE + 0x08, 0}, {ACPI_IO_BASE + 0x0C, 0}, @@ -86,7 +86,7 @@ struct FLASH_DEVICE { unsigned long fMask; /* Flash size/mask */ }; -struct FLASH_DEVICE FlashInitTable[] = { +static struct FLASH_DEVICE FlashInitTable[] = { {FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K}, /* CS0, or Flash Device 0 */ {FLASH_TYPE_NONE, 0, 0}, /* CS1, or Flash Device 1 */ {FLASH_TYPE_NONE, 0, 0}, /* CS2, or Flash Device 2 */ @@ -95,7 +95,7 @@ struct FLASH_DEVICE FlashInitTable[] = { #define FlashInitTableLen (ARRAY_SIZE(FlashInitTable)) -u32 FlashPort[] = { +static u32 FlashPort[] = { MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LBAR_FLSH2, @@ -512,12 +512,16 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) } } -/* ***************************************************************************/ -/* **/ -/* * ChipsetInit */ -/* Called from northbridge init (Pre-VSA). */ -/* **/ -/* ***************************************************************************/ +/**************************************************************************** + * + * ChipsetInit + * + * Called from northbridge init (Pre-VSA). + * + * NOTE! This function is NOT called if the CS5536 is combined with + * an AMD Geode GX2. It's ONLY used on Geode LX based systems. + * + ****************************************************************************/ void chipsetinit(void) { device_t dev; -- cgit v1.2.3