From 9839cbd53fdcfcee52c406d9f52af924192e618d Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Wed, 21 Apr 2010 20:06:10 +0000 Subject: * clean up all but two warnings on artecgroup dbe61 * integrate vsm init into normal x86.c code (so it can run above 1M) * call void main(unsigned long bist) except void cache_as_ram_main(void) on Geode LX (as we do on almost all other platforms now) * Unify Geode LX MSR setup (will bring most non-working LX targets back to life) Signed-off-by: Stefan Reinauer Acked-by: Patrick Georgi git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/cs5536/cs5536.h | 9 +++++++++ src/southbridge/amd/cs5536/cs5536_early_setup.c | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'src/southbridge/amd/cs5536') diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h index a00709a4a9..073bb3ea59 100644 --- a/src/southbridge/amd/cs5536/cs5536.h +++ b/src/southbridge/amd/cs5536/cs5536.h @@ -464,4 +464,13 @@ #define FLASH_IO_128B 0x0000FF80 #define FLASH_IO_256B 0x0000FF00 +#if !defined(ASSEMBLY) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) +void cs5536_setup_onchipuart(int uart); +void cs5536_disable_internal_uart(void); +#else +void chipsetinit(void); +#endif +#endif + #endif /* _CS5536_H */ diff --git a/src/southbridge/amd/cs5536/cs5536_early_setup.c b/src/southbridge/amd/cs5536/cs5536_early_setup.c index cedc209c56..452e530f41 100644 --- a/src/southbridge/amd/cs5536/cs5536_early_setup.c +++ b/src/southbridge/amd/cs5536/cs5536_early_setup.c @@ -121,7 +121,7 @@ static void cs5536_setup_gpio(void) outl(val, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); } -static void cs5536_disable_internal_uart(void) +void cs5536_disable_internal_uart(void) { msr_t msr; /* The UARTs default to enabled. -- cgit v1.2.3