From 88fb1a6c371c9f368157bdb907f70d46bb670311 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Thu, 22 Jun 2006 04:37:27 +0000 Subject: set up interrupt values for the southbridge, and add a function to manage them. Make pci_level_irq global. Add value settings for OLPC rev_a board. Comment out no-longer-needed code in olpc mainboard.c -- it is replaced by the settings in Config.lb, and the support in cs5536.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/cs5536/chip.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/southbridge/amd/cs5536/chip.h') diff --git a/src/southbridge/amd/cs5536/chip.h b/src/southbridge/amd/cs5536/chip.h index 33cc78a2f1..c186ff31d7 100644 --- a/src/southbridge/amd/cs5536/chip.h +++ b/src/southbridge/amd/cs5536/chip.h @@ -10,6 +10,14 @@ struct southbridge_amd_cs5536_config { int enable_gpio0_inta; /* almost always will be true */ int enable_ide_nand_flash; /* if you are using nand flash instead of IDE drive */ int enable_uarta; /* internal uarta interrupt enable */ + /* following are IRQ numbers for various southbridge resources. */ + /* I have guessed at some things, as I still don't have an lspci from anyone */ + int ide_irq; /* f.2 */ + int audio_irq; /* f.3 */ + int usbf4_irq; /* f.4 */ + int usbf5_irq; /* f.5 */ + int usbf6_irq; /* f.6 */ + int usbf7_irq; /* f.7 */ }; #endif /* _SOUTHBRIDGE_AMD_CS5536 */ -- cgit v1.2.3