From ba28e8d73b143def8dfe7c0dc7cfcbce83c601a1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 31 Aug 2016 19:22:16 +0200 Subject: src/southbridge: Code formating Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/16291 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/southbridge/amd/cs5535/chipsetinit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge/amd/cs5535/chipsetinit.c') diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c index 05fb6eb1da..a6c0084087 100644 --- a/src/southbridge/amd/cs5535/chipsetinit.c +++ b/src/southbridge/amd/cs5535/chipsetinit.c @@ -328,7 +328,7 @@ chipsetinit(void) i = 0; csi = &SB_MASTER_CONF_TABLE[i]; - for(; csi->msrnum; csi++){ + for (; csi->msrnum; csi++){ msr.lo = csi->msr.lo; msr.hi = csi->msr.hi; wrmsr(csi->msrnum, msr); // MSR - see table above @@ -347,7 +347,7 @@ chipsetinit(void) { csi = CS5535_CLOCK_GATING_TABLE; - for(; csi->msrnum; csi++){ + for (; csi->msrnum; csi++){ msr.lo = csi->msr.lo; msr.hi = csi->msr.hi; wrmsr(csi->msrnum, msr); // MSR - see table above -- cgit v1.2.3