From f65c1e40885377a07794fc59f38fce1c9230854f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sun, 1 Dec 2019 18:14:39 +0100 Subject: amdblocks/acpimmio: Unify BIOSRAM usage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All AMD CPU families supported in coreboot have BIOSRAM space. Looking at the source code, every family could have the same API to save and restore cbmem top or UMA base and size. Unify BIOSRAM layout and add implementation for cbmem top and UMA storing. Also replace the existing implementation of cbmem top and UMA with the BIOSRAM access. TEST=boot PC Engines apu1 and apu2 Signed-off-by: Michał Żygowski Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da Reviewed-on: https://review.coreboot.org/c/coreboot/+/37402 Reviewed-by: Richard Spiegel Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/southbridge/amd/cimx/sb800/ramtop.c | 24 ------------------------ 1 file changed, 24 deletions(-) (limited to 'src/southbridge/amd/cimx') diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c index b9fc00df06..98d12c7101 100644 --- a/src/southbridge/amd/cimx/sb800/ramtop.c +++ b/src/southbridge/amd/cimx/sb800/ramtop.c @@ -25,27 +25,3 @@ int acpi_get_sleep_type(void) tmp = ((tmp & (7 << 10)) >> 10); return (int)tmp; } - -void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - u32 dword = ramtop; - int nvram_pos = 0xf8, i; /* temp */ - for (i = 0; i < 4; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - u32 xdata = 0; - int xnvram_pos = 0xf8, xi; - for (xi = 0; xi < 4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi * 8); - xnvram_pos++; - } - return xdata; -} -- cgit v1.2.3