From e61dd0f7a2be83ce5ba87d74f7384111576ffd49 Mon Sep 17 00:00:00 2001
From: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date: Tue, 6 May 2014 23:53:09 +1000
Subject: southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridge
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We should configure i8254/i8259 down in to the southbridge rather than
romstage of every AGESA/CIMx board much like Intel boards do.

Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5669
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
 src/southbridge/amd/cimx/sb800/late.c | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/southbridge/amd/cimx/sb800/late.c')

diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 219118aa25..40b422bc83 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -24,6 +24,8 @@
 #include <arch/ioapic.h>
 #include <device/smbus.h>	/* smbus_bus_operations */
 #include <pc80/mc146818rtc.h>
+#include <pc80/i8254.h>
+#include <pc80/i8259.h>
 #include <console/console.h>	/* printk */
 #include <arch/acpi.h>
 #include <device/pci_ehci.h>
@@ -136,6 +138,9 @@ static void lpc_init(device_t dev)
 	 */
 	rtc_init(0);
 
+	setup_i8259(); /* Initialize i8259 pic */
+	setup_i8254(); /* Initialize i8254 timers */
+
 	printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n");
 }
 
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