From 04506e2987162ec0f280afddd6f4acac070bbf15 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 19:28:19 +0200 Subject: sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register Change-Id: I779387fb0c9d3ad6e16d4ccfc39c38dfe6620345 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40806 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/amd/cimx/sb800/late.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/southbridge/amd/cimx/sb800/late.c') diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 1cf3ae8d00..de91a9af51 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -98,7 +98,7 @@ static void ahci_raid_init(struct device *dev) } dev->command |= PCI_COMMAND_MASTER; - pci_write_config8(dev, PCI_COMMAND, dev->command); + pci_write_config16(dev, PCI_COMMAND, dev->command); printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); } -- cgit v1.2.3