From c0733e1639bc97cd1774c556edd6bb6526876529 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sun, 14 Feb 2021 06:58:39 +0200 Subject: ACPI: Use common OperationRegion for PCI_MMCONF MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Iadb4c3c77ecda4df8e48415d246e769ede2ce86d Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/50648 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/southbridge/amd/cimx/sb800/acpi/pcie.asl | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/southbridge/amd/cimx/sb800/acpi') diff --git a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl index 65ac920efa..f69ba1db24 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl @@ -29,9 +29,7 @@ Scope(\) { } Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { + Field(PCFG, ByteAcc, NoLock, Preserve) { /* Byte offsets are computed using the following technique: * ((bus number + 1) * ((device number * 8) * 4096)) + register offset * The 8 comes from 8 functions per device, and 4096 bytes per function config space -- cgit v1.2.3