From 836ae29ee325b1e3d28ff59468cc50913b1e24ce Mon Sep 17 00:00:00 2001 From: stepan Date: Wed, 8 Dec 2010 05:42:47 +0000 Subject: first round name simplification. drop the _ prefix. the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the _ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: Acked-by: Patrick Georgi Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/amd8111/Makefile.inc | 20 +- src/southbridge/amd/amd8111/ac97.c | 52 +++++ src/southbridge/amd/amd8111/acpi.c | 220 ++++++++++++++++++++++ src/southbridge/amd/amd8111/amd8111_ac97.c | 52 ----- src/southbridge/amd/amd8111/amd8111_acpi.c | 220 ---------------------- src/southbridge/amd/amd8111/amd8111_early_ctrl.c | 83 -------- src/southbridge/amd/amd8111/amd8111_early_smbus.c | 48 ----- src/southbridge/amd/amd8111/amd8111_enable_rom.c | 42 ----- src/southbridge/amd/amd8111/amd8111_ide.c | 66 ------- src/southbridge/amd/amd8111/amd8111_lpc.c | 133 ------------- src/southbridge/amd/amd8111/amd8111_nic.c | 90 --------- src/southbridge/amd/amd8111/amd8111_pci.c | 68 ------- src/southbridge/amd/amd8111/amd8111_reset.c | 76 -------- src/southbridge/amd/amd8111/amd8111_smbus.c | 41 ---- src/southbridge/amd/amd8111/amd8111_usb.c | 37 ---- src/southbridge/amd/amd8111/amd8111_usb2.c | 45 ----- src/southbridge/amd/amd8111/bootblock.c | 2 +- src/southbridge/amd/amd8111/early_ctrl.c | 83 ++++++++ src/southbridge/amd/amd8111/early_smbus.c | 48 +++++ src/southbridge/amd/amd8111/enable_rom.c | 42 +++++ src/southbridge/amd/amd8111/ide.c | 66 +++++++ src/southbridge/amd/amd8111/lpc.c | 133 +++++++++++++ src/southbridge/amd/amd8111/nic.c | 90 +++++++++ src/southbridge/amd/amd8111/pci.c | 68 +++++++ src/southbridge/amd/amd8111/reset.c | 76 ++++++++ src/southbridge/amd/amd8111/smbus.c | 41 ++++ src/southbridge/amd/amd8111/usb.c | 37 ++++ src/southbridge/amd/amd8111/usb2.c | 45 +++++ 28 files changed, 1012 insertions(+), 1012 deletions(-) create mode 100644 src/southbridge/amd/amd8111/ac97.c create mode 100644 src/southbridge/amd/amd8111/acpi.c delete mode 100644 src/southbridge/amd/amd8111/amd8111_ac97.c delete mode 100644 src/southbridge/amd/amd8111/amd8111_acpi.c delete mode 100644 src/southbridge/amd/amd8111/amd8111_early_ctrl.c delete mode 100644 src/southbridge/amd/amd8111/amd8111_early_smbus.c delete mode 100644 src/southbridge/amd/amd8111/amd8111_enable_rom.c delete mode 100644 src/southbridge/amd/amd8111/amd8111_ide.c delete mode 100644 src/southbridge/amd/amd8111/amd8111_lpc.c delete mode 100644 src/southbridge/amd/amd8111/amd8111_nic.c delete mode 100644 src/southbridge/amd/amd8111/amd8111_pci.c delete mode 100644 src/southbridge/amd/amd8111/amd8111_reset.c delete mode 100644 src/southbridge/amd/amd8111/amd8111_smbus.c delete mode 100644 src/southbridge/amd/amd8111/amd8111_usb.c delete mode 100644 src/southbridge/amd/amd8111/amd8111_usb2.c create mode 100644 src/southbridge/amd/amd8111/early_ctrl.c create mode 100644 src/southbridge/amd/amd8111/early_smbus.c create mode 100644 src/southbridge/amd/amd8111/enable_rom.c create mode 100644 src/southbridge/amd/amd8111/ide.c create mode 100644 src/southbridge/amd/amd8111/lpc.c create mode 100644 src/southbridge/amd/amd8111/nic.c create mode 100644 src/southbridge/amd/amd8111/pci.c create mode 100644 src/southbridge/amd/amd8111/reset.c create mode 100644 src/southbridge/amd/amd8111/smbus.c create mode 100644 src/southbridge/amd/amd8111/usb.c create mode 100644 src/southbridge/amd/amd8111/usb2.c (limited to 'src/southbridge/amd/amd8111') diff --git a/src/southbridge/amd/amd8111/Makefile.inc b/src/southbridge/amd/amd8111/Makefile.inc index b58fbaac88..cdad4a62ab 100644 --- a/src/southbridge/amd/amd8111/Makefile.inc +++ b/src/southbridge/amd/amd8111/Makefile.inc @@ -1,11 +1,11 @@ driver-y += amd8111.c -driver-y += amd8111_usb.c -driver-y += amd8111_lpc.c -driver-y += amd8111_ide.c -driver-y += amd8111_acpi.c -driver-y += amd8111_usb2.c -driver-y += amd8111_ac97.c -driver-y += amd8111_nic.c -driver-y += amd8111_pci.c -driver-y += amd8111_smbus.c -ramstage-y += amd8111_reset.c +driver-y += usb.c +driver-y += lpc.c +driver-y += ide.c +driver-y += acpi.c +driver-y += usb2.c +driver-y += ac97.c +driver-y += nic.c +driver-y += pci.c +driver-y += smbus.c +ramstage-y += reset.c diff --git a/src/southbridge/amd/amd8111/ac97.c b/src/southbridge/amd/amd8111/ac97.c new file mode 100644 index 0000000000..f49c9bfd5f --- /dev/null +++ b/src/southbridge/amd/amd8111/ac97.c @@ -0,0 +1,52 @@ +/* + * (C) 2003 Linux Networx + */ +#include +#include +#include +#include +#include +#include "amd8111.h" + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x2c, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations ac97audio_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = amd8111_enable, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver ac97audio_driver __pci_driver = { + .ops = &ac97audio_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x746D, +}; + + +static struct device_operations ac97modem_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = amd8111_enable, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver ac97modem_driver __pci_driver = { + .ops = &ac97modem_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x746E, +}; diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c new file mode 100644 index 0000000000..2ad54b78f6 --- /dev/null +++ b/src/southbridge/amd/amd8111/acpi.c @@ -0,0 +1,220 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "amd8111.h" +#include "amd8111_smbus.h" + +#define PREVIOUS_POWER_STATE 0x43 +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define SLOW_CPU_OFF 0 +#define SLOW_CPU__ON 1 + +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#endif + + +static int lsmbus_recv_byte(device_t dev) +{ + unsigned device; + struct resource *res; + + device = dev->path.i2c.device; + res = find_resource(get_pbus_smbus(dev)->dev, 0x58); + + return do_smbus_recv_byte(res->base, device); +} + +static int lsmbus_send_byte(device_t dev, uint8_t val) +{ + unsigned device; + struct resource *res; + + device = dev->path.i2c.device; + res = find_resource(get_pbus_smbus(dev)->dev, 0x58); + + return do_smbus_send_byte(res->base, device, val); +} + + +static int lsmbus_read_byte(device_t dev, uint8_t address) +{ + unsigned device; + struct resource *res; + + device = dev->path.i2c.device; + res = find_resource(get_pbus_smbus(dev)->dev, 0x58); + + return do_smbus_read_byte(res->base, device, address); +} + +static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) +{ + unsigned device; + struct resource *res; + + device = dev->path.i2c.device; + res = find_resource(get_pbus_smbus(dev)->dev, 0x58); + + return do_smbus_write_byte(res->base, device, address, val); +} + +#if CONFIG_GENERATE_ACPI_TABLES == 1 +unsigned pm_base; +#endif + +static void acpi_init(struct device *dev) +{ + uint8_t byte; + uint16_t pm10_bar; + uint32_t dword; + int on; + +#if 0 + uint16_t word; + printk(BIOS_DEBUG, "ACPI: disabling NMI watchdog.. "); + byte = pci_read_config8(dev, 0x49); + pci_write_config8(dev, 0x49, byte | (1<<2)); + + + byte = pci_read_config8(dev, 0x41); + pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<2)); + + /* added from sourceforge */ + byte = pci_read_config8(dev, 0x48); + pci_write_config8(dev, 0x48, byte | (1<<3)); + + printk(BIOS_DEBUG, "done.\n"); + + + printk(BIOS_DEBUG, "ACPI: Routing IRQ 12 to PS2 port.. "); + word = pci_read_config16(dev, 0x46); + pci_write_config16(dev, 0x46, word | (1<<9)); + printk(BIOS_DEBUG, "done.\n"); +#endif + + /* To enable the register 0xcf9 in the IO space + * bit [D5] is set in the amd8111 configuration register. + * The config. reg. is devBx41. Register 0xcf9 allows + * hard reset capability to the system. For the ACPI + * reset.reg values in fadt.c to work this register + * must be enabled. + */ + byte = pci_read_config8(dev, 0x41); + pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5)); + + /* power on after power fail */ + on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + get_option(&on, "power_on_after_fail"); + byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); + byte &= ~0x40; + if (!on) { + byte |= 0x40; + } + pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); + printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off"); + + /* switch serial irq logic from quiet mode to continuous + * mode for Winbond W83627HF Rev. 17 + */ + byte = pci_read_config8(dev, 0x4a); + pci_write_config8(dev, 0x4a, byte | (1<<6)); + + /* Throttle the CPU speed down for testing */ + on = SLOW_CPU_OFF; + get_option(&on, "slow_cpu"); + if(on) { + pm10_bar = (pci_read_config16(dev, 0x58)&0xff00); + outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); + dword = inl(pm10_bar + 0x10); + on = 8-on; + printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", + (on*12)+(on>>1),(on&1)*5); + } + +#if CONFIG_GENERATE_ACPI_TABLES == 1 + pm_base = pci_read_config16(dev, 0x58) & 0xff00; + printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base); +#endif + +} + +static void acpi_read_resources(device_t dev) +{ + struct resource *resource; + + /* Handle the generic bars */ + pci_dev_read_resources(dev); + + /* Add the ACPI/SMBUS bar */ + resource = new_resource(dev, 0x58); + resource->base = 0; + resource->size = 256; + resource->align = log2(256); + resource->gran = log2(256); + resource->limit = 65536; + resource->flags = IORESOURCE_IO; + resource->index = 0x58; +} + +static void acpi_enable_resources(device_t dev) +{ + uint8_t byte; + /* Enable the generic pci resources */ + pci_dev_enable_resources(dev); + + /* Enable the ACPI/SMBUS Bar */ + byte = pci_read_config8(dev, 0x41); + byte |= (1 << 7); + pci_write_config8(dev, 0x41, byte); + + /* Set the class code */ + pci_write_config32(dev, 0x60, 0x06800000); + +} + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x7c, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct smbus_bus_operations lops_smbus_bus = { + .recv_byte = lsmbus_recv_byte, + .send_byte = lsmbus_send_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, +}; + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations acpi_ops = { + .read_resources = acpi_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = acpi_enable_resources, + .init = acpi_init, + .scan_bus = scan_static_bus, + /* We don't need amd8111_enable, chip ops takes care of it. + * It could be useful if these devices were not + * enabled by default. + */ +// .enable = amd8111_enable, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, +}; + +static const struct pci_driver acpi_driver __pci_driver = { + .ops = &acpi_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8111_ACPI, +}; + diff --git a/src/southbridge/amd/amd8111/amd8111_ac97.c b/src/southbridge/amd/amd8111/amd8111_ac97.c deleted file mode 100644 index f49c9bfd5f..0000000000 --- a/src/southbridge/amd/amd8111/amd8111_ac97.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) 2003 Linux Networx - */ -#include -#include -#include -#include -#include -#include "amd8111.h" - -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x2c, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations ac97audio_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = amd8111_enable, - .init = 0, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ac97audio_driver __pci_driver = { - .ops = &ac97audio_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x746D, -}; - - -static struct device_operations ac97modem_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = amd8111_enable, - .init = 0, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ac97modem_driver __pci_driver = { - .ops = &ac97modem_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x746E, -}; diff --git a/src/southbridge/amd/amd8111/amd8111_acpi.c b/src/southbridge/amd/amd8111/amd8111_acpi.c deleted file mode 100644 index 2ad54b78f6..0000000000 --- a/src/southbridge/amd/amd8111/amd8111_acpi.c +++ /dev/null @@ -1,220 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "amd8111.h" -#include "amd8111_smbus.h" - -#define PREVIOUS_POWER_STATE 0x43 -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 -#define SLOW_CPU_OFF 0 -#define SLOW_CPU__ON 1 - -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - - -static int lsmbus_recv_byte(device_t dev) -{ - unsigned device; - struct resource *res; - - device = dev->path.i2c.device; - res = find_resource(get_pbus_smbus(dev)->dev, 0x58); - - return do_smbus_recv_byte(res->base, device); -} - -static int lsmbus_send_byte(device_t dev, uint8_t val) -{ - unsigned device; - struct resource *res; - - device = dev->path.i2c.device; - res = find_resource(get_pbus_smbus(dev)->dev, 0x58); - - return do_smbus_send_byte(res->base, device, val); -} - - -static int lsmbus_read_byte(device_t dev, uint8_t address) -{ - unsigned device; - struct resource *res; - - device = dev->path.i2c.device; - res = find_resource(get_pbus_smbus(dev)->dev, 0x58); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) -{ - unsigned device; - struct resource *res; - - device = dev->path.i2c.device; - res = find_resource(get_pbus_smbus(dev)->dev, 0x58); - - return do_smbus_write_byte(res->base, device, address, val); -} - -#if CONFIG_GENERATE_ACPI_TABLES == 1 -unsigned pm_base; -#endif - -static void acpi_init(struct device *dev) -{ - uint8_t byte; - uint16_t pm10_bar; - uint32_t dword; - int on; - -#if 0 - uint16_t word; - printk(BIOS_DEBUG, "ACPI: disabling NMI watchdog.. "); - byte = pci_read_config8(dev, 0x49); - pci_write_config8(dev, 0x49, byte | (1<<2)); - - - byte = pci_read_config8(dev, 0x41); - pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<2)); - - /* added from sourceforge */ - byte = pci_read_config8(dev, 0x48); - pci_write_config8(dev, 0x48, byte | (1<<3)); - - printk(BIOS_DEBUG, "done.\n"); - - - printk(BIOS_DEBUG, "ACPI: Routing IRQ 12 to PS2 port.. "); - word = pci_read_config16(dev, 0x46); - pci_write_config16(dev, 0x46, word | (1<<9)); - printk(BIOS_DEBUG, "done.\n"); -#endif - - /* To enable the register 0xcf9 in the IO space - * bit [D5] is set in the amd8111 configuration register. - * The config. reg. is devBx41. Register 0xcf9 allows - * hard reset capability to the system. For the ACPI - * reset.reg values in fadt.c to work this register - * must be enabled. - */ - byte = pci_read_config8(dev, 0x41); - pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5)); - - /* power on after power fail */ - on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option(&on, "power_on_after_fail"); - byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); - byte &= ~0x40; - if (!on) { - byte |= 0x40; - } - pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); - printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off"); - - /* switch serial irq logic from quiet mode to continuous - * mode for Winbond W83627HF Rev. 17 - */ - byte = pci_read_config8(dev, 0x4a); - pci_write_config8(dev, 0x4a, byte | (1<<6)); - - /* Throttle the CPU speed down for testing */ - on = SLOW_CPU_OFF; - get_option(&on, "slow_cpu"); - if(on) { - pm10_bar = (pci_read_config16(dev, 0x58)&0xff00); - outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); - dword = inl(pm10_bar + 0x10); - on = 8-on; - printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", - (on*12)+(on>>1),(on&1)*5); - } - -#if CONFIG_GENERATE_ACPI_TABLES == 1 - pm_base = pci_read_config16(dev, 0x58) & 0xff00; - printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base); -#endif - -} - -static void acpi_read_resources(device_t dev) -{ - struct resource *resource; - - /* Handle the generic bars */ - pci_dev_read_resources(dev); - - /* Add the ACPI/SMBUS bar */ - resource = new_resource(dev, 0x58); - resource->base = 0; - resource->size = 256; - resource->align = log2(256); - resource->gran = log2(256); - resource->limit = 65536; - resource->flags = IORESOURCE_IO; - resource->index = 0x58; -} - -static void acpi_enable_resources(device_t dev) -{ - uint8_t byte; - /* Enable the generic pci resources */ - pci_dev_enable_resources(dev); - - /* Enable the ACPI/SMBUS Bar */ - byte = pci_read_config8(dev, 0x41); - byte |= (1 << 7); - pci_write_config8(dev, 0x41, byte); - - /* Set the class code */ - pci_write_config32(dev, 0x60, 0x06800000); - -} - -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x7c, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .recv_byte = lsmbus_recv_byte, - .send_byte = lsmbus_send_byte, - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations acpi_ops = { - .read_resources = acpi_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = acpi_enable_resources, - .init = acpi_init, - .scan_bus = scan_static_bus, - /* We don't need amd8111_enable, chip ops takes care of it. - * It could be useful if these devices were not - * enabled by default. - */ -// .enable = amd8111_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, -}; - -static const struct pci_driver acpi_driver __pci_driver = { - .ops = &acpi_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_ACPI, -}; - diff --git a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c b/src/southbridge/amd/amd8111/amd8111_early_ctrl.c deleted file mode 100644 index ece99ed40a..0000000000 --- a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c +++ /dev/null @@ -1,83 +0,0 @@ -#include "amd8111.h" -#include - -/* by yhlu 2005.10 */ -static unsigned get_sbdn(unsigned bus) -{ - device_t dev; - - /* Find the device. - * There can only be one 8111 on a hypertransport chain/bus. - */ - dev = pci_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI), - bus); - - return (dev>>15) & 0x1f; - -} - -static void enable_cf9_x(unsigned sbbusn, unsigned sbdn) -{ - device_t dev; - uint8_t byte; - - dev = PCI_DEV(sbbusn, sbdn+1, 3); //ACPI - /* enable cf9 */ - byte = pci_read_config8(dev, 0x41); - byte |= (1<<6) | (1<<5); - pci_write_config8(dev, 0x41, byte); -} - -static void enable_cf9(void) -{ - unsigned sblk = get_sblk(); - unsigned sbbusn = get_sbbusn(sblk); - unsigned sbdn = get_sbdn(sbbusn); - - enable_cf9_x(sbbusn, sbdn); -} - -void hard_reset(void) -{ - set_bios_reset(); - /* reset */ - enable_cf9(); - outb(0x0e, 0x0cf9); // make sure cf9 is enabled -} - -void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) -{ - device_t dev; - - dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI - - pci_write_config8(dev, 0x74, 4); - - /* set VFSMAF ( VID/FID System Management Action Field) to 2 */ - pci_write_config32(dev, 0x70, 2<<12); - -} - -static void soft_reset_x(unsigned sbbusn, unsigned sbdn) -{ - device_t dev; - - dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA - - /* Reset */ - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); - -} - -void soft_reset(void) -{ - - unsigned sblk = get_sblk(); - unsigned sbbusn = get_sbbusn(sblk); - unsigned sbdn = get_sbdn(sbbusn); - - return soft_reset_x(sbbusn, sbdn); - -} diff --git a/src/southbridge/amd/amd8111/amd8111_early_smbus.c b/src/southbridge/amd/amd8111/amd8111_early_smbus.c deleted file mode 100644 index e6d70847ea..0000000000 --- a/src/southbridge/amd/amd8111/amd8111_early_smbus.c +++ /dev/null @@ -1,48 +0,0 @@ -#include "amd8111_smbus.h" - -#define SMBUS_IO_BASE 0x0f00 - -static void enable_smbus(void) -{ - device_t dev; - uint8_t enable; - - dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0); - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\n"); - } - - pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1); - enable = pci_read_config8(dev, 0x41); - pci_write_config8(dev, 0x41, enable | (1 << 7)); - - /* check that we can see the smbus controller I/O. */ - if (inw(SMBUS_IO_BASE)==0xFF){ - die("SMBUS controller I/O not found\n"); - } - - /* clear any lingering errors, so the transaction will run */ - outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS); - print_spew("SMBus controller enabled\n"); -} - -static inline int smbus_recv_byte(unsigned device) -{ - return do_smbus_recv_byte(SMBUS_IO_BASE, device); -} - -static inline int smbus_send_byte(unsigned device, unsigned char val) -{ - return do_smbus_send_byte(SMBUS_IO_BASE, device, val); -} - -static inline int smbus_read_byte(unsigned device, unsigned address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val) -{ - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); -} - diff --git a/src/southbridge/amd/amd8111/amd8111_enable_rom.c b/src/southbridge/amd/amd8111/amd8111_enable_rom.c deleted file mode 100644 index 3e73112b47..0000000000 --- a/src/southbridge/amd/amd8111/amd8111_enable_rom.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Linux Networx - * (Written by Eric Biederman for Linux Networx) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include - -/* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */ -static void amd8111_enable_rom(void) -{ - u8 byte; - device_t dev; - - dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_8111_ISA), 0); - - /* Note: The 0xFFFF0000 - 0xFFFFFFFF range is always enabled. */ - - /* Set the 5MB enable bits. */ - byte = pci_io_read_config8(dev, 0x43); - byte |= (1 << 7); /* Enable 0xFFC00000-0xFFFFFFFF (4MB). */ - byte |= (1 << 6); /* Enable 0xFFB00000-0xFFBFFFFF (1MB). */ - pci_io_write_config8(dev, 0x43, byte); -} diff --git a/src/southbridge/amd/amd8111/amd8111_ide.c b/src/southbridge/amd/amd8111/amd8111_ide.c deleted file mode 100644 index 3299875187..0000000000 --- a/src/southbridge/amd/amd8111/amd8111_ide.c +++ /dev/null @@ -1,66 +0,0 @@ -#include -#include -#include -#include -#include -#include "amd8111.h" - -static void ide_init(struct device *dev) -{ - struct southbridge_amd_amd8111_config *conf; - /* Enable ide devices so the linux ide driver will work */ - uint16_t word; - uint8_t byte; - conf = dev->chip_info; - - word = pci_read_config16(dev, 0x40); - /* Ensure prefetch is disabled */ - word &= ~((1 << 15) | (1 << 13)); - if (conf->ide1_enable) { - /* Enable secondary ide interface */ - word |= (1<<0); - printk(BIOS_DEBUG, "IDE1 "); - } - if (conf->ide0_enable) { - /* Enable primary ide interface */ - word |= (1<<1); - printk(BIOS_DEBUG, "IDE0 "); - } - - word |= (1<<12); - word |= (1<<14); - - pci_write_config16(dev, 0x40, word); - - - byte = 0x20 ; // Latency: 64-->32 - pci_write_config8(dev, 0xd, byte); - - word = 0x0f; - pci_write_config16(dev, 0x42, word); -} - -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x70, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, - .enable = amd8111_enable, - .ops_pci = &lops_pci -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_IDE, -}; - diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c deleted file mode 100644 index e9bd5fc42b..0000000000 --- a/src/southbridge/amd/amd8111/amd8111_lpc.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * (C) 2003 Linux Networx, SuSE Linux AG - * 2006.1 yhlu add dest apicid for IRQ0 - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "amd8111.h" - -#define NMI_OFF 0 - -static void enable_hpet(struct device *dev) -{ - unsigned long hpet_address; - - pci_write_config32(dev,0xa0, 0xfed00001); - hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe; - printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); - -} - -static void lpc_init(struct device *dev) -{ - uint8_t byte; - int nmi_option; - - /* IO APIC initialization */ - byte = pci_read_config8(dev, 0x4B); - byte |= 1; - pci_write_config8(dev, 0x4B, byte); - /* Don't rename IO APIC */ - setup_ioapic(IO_APIC_ADDR, 0); - - /* posted memory write enable */ - byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1<<0)); - - /* Enable 5Mib Rom window */ - byte = pci_read_config8(dev, 0x43); - byte |= 0xc0; - pci_write_config8(dev, 0x43, byte); - - /* Enable Port 92 fast reset */ - byte = pci_read_config8(dev, 0x41); - byte |= (1 << 5); - pci_write_config8(dev, 0x41, byte); - - /* Enable Error reporting */ - /* Set up sync flood detected */ - byte = pci_read_config8(dev, 0x47); - byte |= (1 << 1); - pci_write_config8(dev, 0x47, byte); - - /* Set up NMI on errors */ - byte = pci_read_config8(dev, 0x40); - byte |= (1 << 1); /* clear PW2LPC error */ - byte |= (1 << 6); /* clear LPCERR */ - pci_write_config8(dev, 0x40, byte); - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - byte |= (1 << 7); /* set NMI */ - pci_write_config8(dev, 0x40, byte); - } - - /* Initialize the real time clock */ - rtc_init(0); - - /* Initialize isa dma */ - isa_dma_init(); - - /* Initialize the High Precision Event Timers */ - enable_hpet(dev); -} - -static void amd8111_lpc_read_resources(device_t dev) -{ - struct resource *res; - - /* Get the normal PCI resources of this device. */ - pci_dev_read_resources(dev); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x70, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations lpc_ops = { - .read_resources = amd8111_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - .enable = amd8111_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_ISA, -}; diff --git a/src/southbridge/amd/amd8111/amd8111_nic.c b/src/southbridge/amd/amd8111/amd8111_nic.c deleted file mode 100644 index 4ab7212eda..0000000000 --- a/src/southbridge/amd/amd8111/amd8111_nic.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * (C) 2003 Linux Networx - */ -#include -#include -#include -#include -#include -#include -#include -#include "amd8111.h" - - -#define CMD3 0x54 - -typedef enum { - VAL3 = (1 << 31), /* VAL bit for byte 3 */ - VAL2 = (1 << 23), /* VAL bit for byte 2 */ - VAL1 = (1 << 15), /* VAL bit for byte 1 */ - VAL0 = (1 << 7), /* VAL bit for byte 0 */ -}VAL_BITS; - -typedef enum { - /* VAL3 */ - ASF_INIT_DONE_ALIAS = (1 << 29), - /* VAL2 */ - JUMBO = (1 << 21), - VSIZE = (1 << 20), - VLONLY = (1 << 19), - VL_TAG_DEL = (1 << 18), - /* VAL1 */ - EN_PMGR = (1 << 14), - INTLEVEL = (1 << 13), - FORCE_FULL_DUPLEX = (1 << 12), - FORCE_LINK_STATUS = (1 << 11), - APEP = (1 << 10), - MPPLBA = (1 << 9), - /* VAL0 */ - RESET_PHY_PULSE = (1 << 2), - RESET_PHY = (1 << 1), - PHY_RST_POL = (1 << 0), -}CMD3_BITS; - -static void nic_init(struct device *dev) -{ - struct southbridge_amd_amd8111_config *conf; - struct resource *resource; - unsigned long mmio; - - conf = dev->chip_info; - resource = find_resource(dev, PCI_BASE_ADDRESS_0); - mmio = resource->base; - - /* Hard Reset PHY */ - printk(BIOS_DEBUG, "Reseting PHY... "); - if (conf->phy_lowreset) { - write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY); - } else { - write32((mmio + CMD3), VAL0 | RESET_PHY); - } - mdelay(15); - write32((mmio + CMD3), RESET_PHY); - printk(BIOS_DEBUG, "Done\n"); -} - -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0xc8, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .scan_bus = 0, - .enable = amd8111_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver nic_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_NIC, -}; diff --git a/src/southbridge/amd/amd8111/amd8111_pci.c b/src/southbridge/amd/amd8111/amd8111_pci.c deleted file mode 100644 index 9e7724980f..0000000000 --- a/src/southbridge/amd/amd8111/amd8111_pci.c +++ /dev/null @@ -1,68 +0,0 @@ -#include -#include -#include -#include -#include -#include "amd8111.h" - -static void pci_init(struct device *dev) -{ - - /* Enable pci error detecting */ - uint32_t dword; - - /* System error enable */ - dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); /* System error enable */ - dword |= (7<<28); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); - - /* System,Parity,timer,and abort error enable */ - dword = pci_read_config32(dev, 0x3c); - dword |= (1<<16); /* Parity */ - dword |= (1<<17); /* System */ - dword |= (1<<21); /* Master abort */ -// dword &= ~(1<<21); /* Master abort */ -// dword |= (1<<27); /* Discard timer */ - dword &= ~(1<<27); /* Discard timer */ - dword |= (1<<26); /* DTSTAT error clear */ - pci_write_config32(dev, 0x3c, dword); - - /* CRC flood enable */ - dword = pci_read_config32(dev, 0xc4); - dword |= (1<<1); /* CRC Flood enable */ - dword |= (1<<8); /* Clear any CRC errors */ - dword |= (1<<4); /* Clear any LKFAIL errors */ - pci_write_config32(dev, 0xc4, dword); - - /* Clear possible errors */ - dword = pci_read_config32(dev, 0x1c); - dword |= (1<<27); /* STA */ - dword |= (1<<28); /* RTA */ - dword |= (1<<29); /* RMA */ - dword |= (1<<30); /* RSE */ - dword |= (1<<31); /* DPE */ - dword |= (1<<24); /* MDPE */ - pci_write_config32(dev, 0x1c, dword); -} - -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, - /* PCI Subordinate bus reset is not implemented */ - .ops_pci = &lops_pci, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_PCI, -}; - diff --git a/src/southbridge/amd/amd8111/amd8111_reset.c b/src/southbridge/amd/amd8111/amd8111_reset.c deleted file mode 100644 index c96e898aea..0000000000 --- a/src/southbridge/amd/amd8111/amd8111_reset.c +++ /dev/null @@ -1,76 +0,0 @@ -#include -#include -#include - -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) - -typedef unsigned device_t; - -static void pci_write_config8(device_t dev, unsigned where, unsigned char value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - -#define PCI_DEV_INVALID (0xffffffffU) -static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) -{ - device_t dev, last; - dev = PCI_DEV(bus, 0, 0); - last = PCI_DEV(bus, 31, 7); - for(; dev <= last; dev += PCI_DEV(0,0,1)) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return PCI_DEV_INVALID; -} - -#include "../../../northbridge/amd/amdk8/reset_test.c" - - -void hard_reset(void) -{ - device_t dev; - unsigned bus; - unsigned node = 0; - unsigned link = get_sblk(); - - /* Find the device. - * There can only be one 8111 on a hypertransport chain/bus. - */ - bus = node_link_to_bus(node, link); - dev = pci_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA), - bus); - - /* Reset */ - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.c b/src/southbridge/amd/amd8111/amd8111_smbus.c deleted file mode 100644 index 0a0c58dce3..0000000000 --- a/src/southbridge/amd/amd8111/amd8111_smbus.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) 2004 Linux Networx - */ -#include -#include -#include -#include -#include -#include -#include -#include "amd8111.h" - - -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x44, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct smbus_bus_operations lops_smbus_bus = { - /* I haven't seen the 2.0 SMBUS controller used yet. */ -}; -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; -static struct device_operations smbus_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_static_bus, - .enable = amd8111_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, -}; - -static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_SMB, -}; diff --git a/src/southbridge/amd/amd8111/amd8111_usb.c b/src/southbridge/amd/amd8111/amd8111_usb.c deleted file mode 100644 index 13dccf435b..0000000000 --- a/src/southbridge/amd/amd8111/amd8111_usb.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) 2004 Linux Networx - */ -#include -#include -#include -#include -#include -#include -#include "amd8111.h" - - -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x70, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations usb_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_static_bus, -// .enable = amd8111_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver usb_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_USB, -}; diff --git a/src/southbridge/amd/amd8111/amd8111_usb2.c b/src/southbridge/amd/amd8111/amd8111_usb2.c deleted file mode 100644 index 89115c3bbe..0000000000 --- a/src/southbridge/amd/amd8111/amd8111_usb2.c +++ /dev/null @@ -1,45 +0,0 @@ -//2003 Copywright Tyan - -#include -#include -#include -#include -#include -#include "amd8111.h" - -#if 0 - -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x70, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -#endif - -static void amd8111_usb2_enable(device_t dev) -{ - // Due to buggy USB2 we force it to disable. - dev->enabled = 0; - amd8111_enable(dev); - printk(BIOS_DEBUG, "USB2 disabled.\n"); -} - -static struct device_operations usb2_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .scan_bus = 0, - .enable = amd8111_usb2_enable, - // .ops_pci = &lops_pci, -}; - -static const struct pci_driver usb2_driver __pci_driver = { - .ops = &usb2_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_USB2, -}; diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c index 695f49898b..a11d1d30f4 100644 --- a/src/southbridge/amd/amd8111/bootblock.c +++ b/src/southbridge/amd/amd8111/bootblock.c @@ -1,4 +1,4 @@ -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" +#include "southbridge/amd/amd8111/enable_rom.c" static void bootblock_southbridge_init(void) { diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c new file mode 100644 index 0000000000..ece99ed40a --- /dev/null +++ b/src/southbridge/amd/amd8111/early_ctrl.c @@ -0,0 +1,83 @@ +#include "amd8111.h" +#include + +/* by yhlu 2005.10 */ +static unsigned get_sbdn(unsigned bus) +{ + device_t dev; + + /* Find the device. + * There can only be one 8111 on a hypertransport chain/bus. + */ + dev = pci_locate_device_on_bus( + PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI), + bus); + + return (dev>>15) & 0x1f; + +} + +static void enable_cf9_x(unsigned sbbusn, unsigned sbdn) +{ + device_t dev; + uint8_t byte; + + dev = PCI_DEV(sbbusn, sbdn+1, 3); //ACPI + /* enable cf9 */ + byte = pci_read_config8(dev, 0x41); + byte |= (1<<6) | (1<<5); + pci_write_config8(dev, 0x41, byte); +} + +static void enable_cf9(void) +{ + unsigned sblk = get_sblk(); + unsigned sbbusn = get_sbbusn(sblk); + unsigned sbdn = get_sbdn(sbbusn); + + enable_cf9_x(sbbusn, sbdn); +} + +void hard_reset(void) +{ + set_bios_reset(); + /* reset */ + enable_cf9(); + outb(0x0e, 0x0cf9); // make sure cf9 is enabled +} + +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +{ + device_t dev; + + dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI + + pci_write_config8(dev, 0x74, 4); + + /* set VFSMAF ( VID/FID System Management Action Field) to 2 */ + pci_write_config32(dev, 0x70, 2<<12); + +} + +static void soft_reset_x(unsigned sbbusn, unsigned sbdn) +{ + device_t dev; + + dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA + + /* Reset */ + set_bios_reset(); + pci_write_config8(dev, 0x47, 1); + +} + +void soft_reset(void) +{ + + unsigned sblk = get_sblk(); + unsigned sbbusn = get_sbbusn(sblk); + unsigned sbdn = get_sbdn(sbbusn); + + return soft_reset_x(sbbusn, sbdn); + +} diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c new file mode 100644 index 0000000000..e6d70847ea --- /dev/null +++ b/src/southbridge/amd/amd8111/early_smbus.c @@ -0,0 +1,48 @@ +#include "amd8111_smbus.h" + +#define SMBUS_IO_BASE 0x0f00 + +static void enable_smbus(void) +{ + device_t dev; + uint8_t enable; + + dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0); + if (dev == PCI_DEV_INVALID) { + die("SMBUS controller not found\n"); + } + + pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1); + enable = pci_read_config8(dev, 0x41); + pci_write_config8(dev, 0x41, enable | (1 << 7)); + + /* check that we can see the smbus controller I/O. */ + if (inw(SMBUS_IO_BASE)==0xFF){ + die("SMBUS controller I/O not found\n"); + } + + /* clear any lingering errors, so the transaction will run */ + outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS); + print_spew("SMBus controller enabled\n"); +} + +static inline int smbus_recv_byte(unsigned device) +{ + return do_smbus_recv_byte(SMBUS_IO_BASE, device); +} + +static inline int smbus_send_byte(unsigned device, unsigned char val) +{ + return do_smbus_send_byte(SMBUS_IO_BASE, device, val); +} + +static inline int smbus_read_byte(unsigned device, unsigned address) +{ + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); +} + +static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val) +{ + return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); +} + diff --git a/src/southbridge/amd/amd8111/enable_rom.c b/src/southbridge/amd/amd8111/enable_rom.c new file mode 100644 index 0000000000..3e73112b47 --- /dev/null +++ b/src/southbridge/amd/amd8111/enable_rom.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Linux Networx + * (Written by Eric Biederman for Linux Networx) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + +/* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */ +static void amd8111_enable_rom(void) +{ + u8 byte; + device_t dev; + + dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_8111_ISA), 0); + + /* Note: The 0xFFFF0000 - 0xFFFFFFFF range is always enabled. */ + + /* Set the 5MB enable bits. */ + byte = pci_io_read_config8(dev, 0x43); + byte |= (1 << 7); /* Enable 0xFFC00000-0xFFFFFFFF (4MB). */ + byte |= (1 << 6); /* Enable 0xFFB00000-0xFFBFFFFF (1MB). */ + pci_io_write_config8(dev, 0x43, byte); +} diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c new file mode 100644 index 0000000000..3299875187 --- /dev/null +++ b/src/southbridge/amd/amd8111/ide.c @@ -0,0 +1,66 @@ +#include +#include +#include +#include +#include +#include "amd8111.h" + +static void ide_init(struct device *dev) +{ + struct southbridge_amd_amd8111_config *conf; + /* Enable ide devices so the linux ide driver will work */ + uint16_t word; + uint8_t byte; + conf = dev->chip_info; + + word = pci_read_config16(dev, 0x40); + /* Ensure prefetch is disabled */ + word &= ~((1 << 15) | (1 << 13)); + if (conf->ide1_enable) { + /* Enable secondary ide interface */ + word |= (1<<0); + printk(BIOS_DEBUG, "IDE1 "); + } + if (conf->ide0_enable) { + /* Enable primary ide interface */ + word |= (1<<1); + printk(BIOS_DEBUG, "IDE0 "); + } + + word |= (1<<12); + word |= (1<<14); + + pci_write_config16(dev, 0x40, word); + + + byte = 0x20 ; // Latency: 64-->32 + pci_write_config8(dev, 0xd, byte); + + word = 0x0f; + pci_write_config16(dev, 0x42, word); +} + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x70, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .scan_bus = 0, + .enable = amd8111_enable, + .ops_pci = &lops_pci +}; + +static const struct pci_driver ide_driver __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8111_IDE, +}; + diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c new file mode 100644 index 0000000000..e9bd5fc42b --- /dev/null +++ b/src/southbridge/amd/amd8111/lpc.c @@ -0,0 +1,133 @@ +/* + * (C) 2003 Linux Networx, SuSE Linux AG + * 2006.1 yhlu add dest apicid for IRQ0 + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "amd8111.h" + +#define NMI_OFF 0 + +static void enable_hpet(struct device *dev) +{ + unsigned long hpet_address; + + pci_write_config32(dev,0xa0, 0xfed00001); + hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe; + printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); + +} + +static void lpc_init(struct device *dev) +{ + uint8_t byte; + int nmi_option; + + /* IO APIC initialization */ + byte = pci_read_config8(dev, 0x4B); + byte |= 1; + pci_write_config8(dev, 0x4B, byte); + /* Don't rename IO APIC */ + setup_ioapic(IO_APIC_ADDR, 0); + + /* posted memory write enable */ + byte = pci_read_config8(dev, 0x46); + pci_write_config8(dev, 0x46, byte | (1<<0)); + + /* Enable 5Mib Rom window */ + byte = pci_read_config8(dev, 0x43); + byte |= 0xc0; + pci_write_config8(dev, 0x43, byte); + + /* Enable Port 92 fast reset */ + byte = pci_read_config8(dev, 0x41); + byte |= (1 << 5); + pci_write_config8(dev, 0x41, byte); + + /* Enable Error reporting */ + /* Set up sync flood detected */ + byte = pci_read_config8(dev, 0x47); + byte |= (1 << 1); + pci_write_config8(dev, 0x47, byte); + + /* Set up NMI on errors */ + byte = pci_read_config8(dev, 0x40); + byte |= (1 << 1); /* clear PW2LPC error */ + byte |= (1 << 6); /* clear LPCERR */ + pci_write_config8(dev, 0x40, byte); + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + byte |= (1 << 7); /* set NMI */ + pci_write_config8(dev, 0x40, byte); + } + + /* Initialize the real time clock */ + rtc_init(0); + + /* Initialize isa dma */ + isa_dma_init(); + + /* Initialize the High Precision Event Timers */ + enable_hpet(dev); +} + +static void amd8111_lpc_read_resources(device_t dev) +{ + struct resource *res; + + /* Get the normal PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = IO_APIC_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x70, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations lpc_ops = { + .read_resources = amd8111_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = lpc_init, + .scan_bus = scan_static_bus, + .enable = amd8111_enable, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8111_ISA, +}; diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c new file mode 100644 index 0000000000..4ab7212eda --- /dev/null +++ b/src/southbridge/amd/amd8111/nic.c @@ -0,0 +1,90 @@ +/* + * (C) 2003 Linux Networx + */ +#include +#include +#include +#include +#include +#include +#include +#include "amd8111.h" + + +#define CMD3 0x54 + +typedef enum { + VAL3 = (1 << 31), /* VAL bit for byte 3 */ + VAL2 = (1 << 23), /* VAL bit for byte 2 */ + VAL1 = (1 << 15), /* VAL bit for byte 1 */ + VAL0 = (1 << 7), /* VAL bit for byte 0 */ +}VAL_BITS; + +typedef enum { + /* VAL3 */ + ASF_INIT_DONE_ALIAS = (1 << 29), + /* VAL2 */ + JUMBO = (1 << 21), + VSIZE = (1 << 20), + VLONLY = (1 << 19), + VL_TAG_DEL = (1 << 18), + /* VAL1 */ + EN_PMGR = (1 << 14), + INTLEVEL = (1 << 13), + FORCE_FULL_DUPLEX = (1 << 12), + FORCE_LINK_STATUS = (1 << 11), + APEP = (1 << 10), + MPPLBA = (1 << 9), + /* VAL0 */ + RESET_PHY_PULSE = (1 << 2), + RESET_PHY = (1 << 1), + PHY_RST_POL = (1 << 0), +}CMD3_BITS; + +static void nic_init(struct device *dev) +{ + struct southbridge_amd_amd8111_config *conf; + struct resource *resource; + unsigned long mmio; + + conf = dev->chip_info; + resource = find_resource(dev, PCI_BASE_ADDRESS_0); + mmio = resource->base; + + /* Hard Reset PHY */ + printk(BIOS_DEBUG, "Reseting PHY... "); + if (conf->phy_lowreset) { + write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY); + } else { + write32((mmio + CMD3), VAL0 | RESET_PHY); + } + mdelay(15); + write32((mmio + CMD3), RESET_PHY); + printk(BIOS_DEBUG, "Done\n"); +} + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0xc8, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .scan_bus = 0, + .enable = amd8111_enable, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver nic_driver __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8111_NIC, +}; diff --git a/src/southbridge/amd/amd8111/pci.c b/src/southbridge/amd/amd8111/pci.c new file mode 100644 index 0000000000..9e7724980f --- /dev/null +++ b/src/southbridge/amd/amd8111/pci.c @@ -0,0 +1,68 @@ +#include +#include +#include +#include +#include +#include "amd8111.h" + +static void pci_init(struct device *dev) +{ + + /* Enable pci error detecting */ + uint32_t dword; + + /* System error enable */ + dword = pci_read_config32(dev, 0x04); + dword |= (1<<8); /* System error enable */ + dword |= (7<<28); /* Clear possible errors */ + pci_write_config32(dev, 0x04, dword); + + /* System,Parity,timer,and abort error enable */ + dword = pci_read_config32(dev, 0x3c); + dword |= (1<<16); /* Parity */ + dword |= (1<<17); /* System */ + dword |= (1<<21); /* Master abort */ +// dword &= ~(1<<21); /* Master abort */ +// dword |= (1<<27); /* Discard timer */ + dword &= ~(1<<27); /* Discard timer */ + dword |= (1<<26); /* DTSTAT error clear */ + pci_write_config32(dev, 0x3c, dword); + + /* CRC flood enable */ + dword = pci_read_config32(dev, 0xc4); + dword |= (1<<1); /* CRC Flood enable */ + dword |= (1<<8); /* Clear any CRC errors */ + dword |= (1<<4); /* Clear any LKFAIL errors */ + pci_write_config32(dev, 0xc4, dword); + + /* Clear possible errors */ + dword = pci_read_config32(dev, 0x1c); + dword |= (1<<27); /* STA */ + dword |= (1<<28); /* RTA */ + dword |= (1<<29); /* RMA */ + dword |= (1<<30); /* RSE */ + dword |= (1<<31); /* DPE */ + dword |= (1<<24); /* MDPE */ + pci_write_config32(dev, 0x1c, dword); +} + +static struct pci_operations lops_pci = { + .set_subsystem = 0, +}; + +static struct device_operations pci_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pci_init, + .scan_bus = pci_scan_bridge, + /* PCI Subordinate bus reset is not implemented */ + .ops_pci = &lops_pci, +}; + +static const struct pci_driver pci_driver __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8111_PCI, +}; + diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c new file mode 100644 index 0000000000..c96e898aea --- /dev/null +++ b/src/southbridge/amd/amd8111/reset.c @@ -0,0 +1,76 @@ +#include +#include +#include + +#define PCI_DEV(BUS, DEV, FN) ( \ + (((BUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x7) << 12)) + +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) + +typedef unsigned device_t; + +static void pci_write_config8(device_t dev, unsigned where, unsigned char value) +{ + unsigned addr; + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outb(value, 0xCFC + (addr & 3)); +} + +static void pci_write_config32(device_t dev, unsigned where, unsigned value) +{ + unsigned addr; + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); +} + +static unsigned pci_read_config32(device_t dev, unsigned where) +{ + unsigned addr; + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); +} + +#define PCI_DEV_INVALID (0xffffffffU) +static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) +{ + device_t dev, last; + dev = PCI_DEV(bus, 0, 0); + last = PCI_DEV(bus, 31, 7); + for(; dev <= last; dev += PCI_DEV(0,0,1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) { + return dev; + } + } + return PCI_DEV_INVALID; +} + +#include "../../../northbridge/amd/amdk8/reset_test.c" + + +void hard_reset(void) +{ + device_t dev; + unsigned bus; + unsigned node = 0; + unsigned link = get_sblk(); + + /* Find the device. + * There can only be one 8111 on a hypertransport chain/bus. + */ + bus = node_link_to_bus(node, link); + dev = pci_locate_device_on_bus( + PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA), + bus); + + /* Reset */ + set_bios_reset(); + pci_write_config8(dev, 0x47, 1); +} diff --git a/src/southbridge/amd/amd8111/smbus.c b/src/southbridge/amd/amd8111/smbus.c new file mode 100644 index 0000000000..0a0c58dce3 --- /dev/null +++ b/src/southbridge/amd/amd8111/smbus.c @@ -0,0 +1,41 @@ +/* + * (C) 2004 Linux Networx + */ +#include +#include +#include +#include +#include +#include +#include +#include "amd8111.h" + + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x44, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct smbus_bus_operations lops_smbus_bus = { + /* I haven't seen the 2.0 SMBUS controller used yet. */ +}; +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; +static struct device_operations smbus_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = scan_static_bus, + .enable = amd8111_enable, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, +}; + +static const struct pci_driver smbus_driver __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8111_SMB, +}; diff --git a/src/southbridge/amd/amd8111/usb.c b/src/southbridge/amd/amd8111/usb.c new file mode 100644 index 0000000000..13dccf435b --- /dev/null +++ b/src/southbridge/amd/amd8111/usb.c @@ -0,0 +1,37 @@ +/* + * (C) 2004 Linux Networx + */ +#include +#include +#include +#include +#include +#include +#include "amd8111.h" + + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x70, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = scan_static_bus, +// .enable = amd8111_enable, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver usb_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8111_USB, +}; diff --git a/src/southbridge/amd/amd8111/usb2.c b/src/southbridge/amd/amd8111/usb2.c new file mode 100644 index 0000000000..89115c3bbe --- /dev/null +++ b/src/southbridge/amd/amd8111/usb2.c @@ -0,0 +1,45 @@ +//2003 Copywright Tyan + +#include +#include +#include +#include +#include +#include "amd8111.h" + +#if 0 + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x70, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +#endif + +static void amd8111_usb2_enable(device_t dev) +{ + // Due to buggy USB2 we force it to disable. + dev->enabled = 0; + amd8111_enable(dev); + printk(BIOS_DEBUG, "USB2 disabled.\n"); +} + +static struct device_operations usb2_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = 0, + .enable = amd8111_usb2_enable, + // .ops_pci = &lops_pci, +}; + +static const struct pci_driver usb2_driver __pci_driver = { + .ops = &usb2_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8111_USB2, +}; -- cgit v1.2.3