From 63fac81fc80d701a785ed61a3b5738ea0a821169 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 2 Sep 2017 16:41:43 +0300 Subject: AGESA: Implement POSTCAR_STAGE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move all boards that have moved away from AGESA_LEGACY_WRAPPER or BINARYPI_LEGACY_WRAPPER to use POSTCAR_STAGE. We use POSTCAR_STAGE as a conditional in CAR teardown to tell our MTRR setup is prepared such that invalidation without writeback is a valid operation. Change-Id: I3f4e2170054bdb84c72d2f7c956f8d51a6d7f0ca Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/21384 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/southbridge/amd/agesa/hudson/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/southbridge/amd/agesa') diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 89236a6c0a..2bf6f02539 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -24,6 +24,7 @@ ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += resume.c ramtop.c romstage-y += ramtop.c +postcar-y += ramtop.c romstage-y += imc.c ramstage-y += imc.c -- cgit v1.2.3