From 08311f5033e3adccb8794b6113d72bf7a76e4d00 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Tue, 19 Apr 2016 07:17:59 +0300
Subject: AGESA vendorcode: Build a common amdlib
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Having CFLAGS with -Os disables -falign-function, for
unlucky builds this may delay entry to ramstage by 600ms.
Build the low-level IO functions aligned with -O2 instead.

Change-Id: Ice6781666a0834f1e8e60a0c93048ac8472f27d9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14414
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/southbridge/amd/agesa/hudson/imc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/southbridge/amd/agesa')

diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c
index a077adee8d..4da6814c68 100644
--- a/src/southbridge/amd/agesa/hudson/imc.c
+++ b/src/southbridge/amd/agesa/hudson/imc.c
@@ -18,7 +18,7 @@
 #include <delay.h>
 #include "Porting.h"
 #include "AGESA.h"
-#include <Lib/amdlib.h>
+#include <amdlib.h>
 #include <Proc/Fch/Fch.h>
 #include <Proc/Fch/Common/FchCommonCfg.h>
 #include <Proc/Fch/FchPlatform.h>
-- 
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