From cd49cce7b70e80b4acc49b56bb2bb94370b4d867 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 5 Mar 2019 16:53:33 -0800 Subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/amd/agesa/hudson/acpi/fch.asl | 8 ++++---- src/southbridge/amd/agesa/hudson/acpi/usb.asl | 4 ++-- src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h | 8 ++++---- src/southbridge/amd/agesa/hudson/amd_pci_int_types.h | 4 ++-- src/southbridge/amd/agesa/hudson/fadt.c | 4 ++-- src/southbridge/amd/agesa/hudson/hudson.c | 6 +++--- src/southbridge/amd/agesa/hudson/imc.c | 4 ++-- src/southbridge/amd/agesa/hudson/lpc.c | 2 +- src/southbridge/amd/agesa/hudson/pci_devs.h | 4 ++-- src/southbridge/amd/agesa/hudson/resume.c | 2 +- src/southbridge/amd/agesa/hudson/sata.c | 2 +- src/southbridge/amd/agesa/hudson/spi.c | 8 ++++---- 12 files changed, 28 insertions(+), 28 deletions(-) (limited to 'src/southbridge/amd/agesa/hudson') diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index 83e3410ccb..825e35464e 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -58,7 +58,7 @@ Device(SDCN) { Name(_ADR, 0x00140007) } /* end SDCN */ -#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) /* 0:14.4 - PCI slot 1, 2, 3 */ Device(PIBR) { @@ -146,7 +146,7 @@ Method(_CRS, 0) { Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#if CONFIG(HUDSON_IMC_FWM) #include "acpi/AmdImc.asl" /* Hudson IMC function */ #endif @@ -175,8 +175,8 @@ Method(_INI, 0) { /* Determine the OS we're running on */ OSFL() -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) -#if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE) +#if CONFIG(HUDSON_IMC_FWM) +#if CONFIG(ACPI_ENABLE_THERMAL_ZONE) ITZE() /* enable IMC Fan Control*/ #endif #endif diff --git a/src/southbridge/amd/agesa/hudson/acpi/usb.asl b/src/southbridge/amd/agesa/hudson/acpi/usb.asl index d83b935ffa..cc07565795 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/usb.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/usb.asl @@ -50,7 +50,7 @@ Device(UOH6) { Name(_PRW, Package() {0x0B, 3}) } /* end UOH5 */ -#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) /* 0:14.5 - OHCI */ Device(UEH1) { Name(_ADR, 0x00140005) @@ -64,7 +64,7 @@ Device(XHC0) { Name(_PRW, Package() {0x0B, 4}) } /* end XHC0 */ -#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) /* 0:10.1 - XHCI 1*/ Device(XHC1) { Name(_ADR, 0x00100001) diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h index 148bcccfc9..ee55be174f 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h @@ -21,9 +21,9 @@ * into the FCH PCI_INTR 0xC00/0xC01 interrupt * routing table */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) #define FCH_INT_TABLE_SIZE 0x54 -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#elif CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) #define FCH_INT_TABLE_SIZE 0x42 #endif @@ -51,7 +51,7 @@ #define PIRQ_FC 0x14 /* FC */ #define PIRQ_GEC 0x15 /* GEC */ #define PIRQ_PMON 0x16 /* Performance Monitor */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) #define PIRQ_SD 0x17 /* SD */ #endif #define PIRQ_IMC0 0x20 /* IMC INT0 */ @@ -69,7 +69,7 @@ #define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ #define PIRQ_IDE 0x40 /* IDE 14h.1 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) #define PIRQ_SD 0x42 /* SD 14h.7 */ #define PIRQ_GPP0 0x50 /* GPP INT 0 */ #define PIRQ_GPP1 0x51 /* GPP INT 1 */ diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h index 7d3ad07205..1b33a0c9c8 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h @@ -16,7 +16,7 @@ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) const char *intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", @@ -26,7 +26,7 @@ const char *intr_types[] = { [0x40] = "IDE\t", "SATA\t", [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t" }; -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#elif CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) const char *intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 230c89f473..28f035c3b8 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -27,7 +27,7 @@ #include "hudson.h" #include "smi.h" -#if IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE) +#if CONFIG(HUDSON_LEGACY_FREE) #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE #else #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) @@ -71,7 +71,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { fadt->smi_cmd = ACPI_SMI_CTL_PORT; fadt->acpi_enable = ACPI_SMI_CMD_ENABLE; fadt->acpi_disable = ACPI_SMI_CMD_DISABLE; diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 8ae685e37d..25997d2e9d 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -154,7 +154,7 @@ static void hudson_init_acpi_ports(void) /* CpuControl is in \_PR.CP00, 6 bytes */ pm_write16(0x66, ACPI_CPU_CONTROL); - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { pm_write16(0x6a, ACPI_SMI_CTL_PORT); hudson_enable_acpi_cmd_smi(); } else { @@ -175,8 +175,8 @@ static void hudson_init(void *chip_info) static void hudson_final(void *chip_info) { /* AMD AGESA does not enable thermal zone, so we enable it here. */ - if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM) && - !IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)) + if (CONFIG(HUDSON_IMC_FWM) && + !CONFIG(ACPI_ENABLE_THERMAL_ZONE)) enable_imc_thermal_zone(); } diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c index 606a529c94..68ff7fb6e3 100644 --- a/src/southbridge/amd/agesa/hudson/imc.c +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -35,7 +35,7 @@ void imc_reg_init(void) write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x03, 0xff); write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x04, 0xff); -#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x10, 0x06); write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x11, 0x06); write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x12, 0xf7); @@ -43,7 +43,7 @@ void imc_reg_init(void) write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x14, 0xff); #endif -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) UINT8 PciData; PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index bf231f8a47..9b18315c5a 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -343,7 +343,7 @@ static struct device_operations lpc_ops = { .read_resources = hudson_lpc_read_resources, .set_resources = hudson_lpc_set_resources, .enable_resources = hudson_lpc_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h index c6528aefba..3406051414 100644 --- a/src/southbridge/amd/agesa/hudson/pci_devs.h +++ b/src/southbridge/amd/agesa/hudson/pci_devs.h @@ -68,7 +68,7 @@ #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) /* IDE */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) #define IDE_DEV 0x14 #define IDE_FUNC 1 # define IDE_DEVID 0x780C @@ -101,7 +101,7 @@ #define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) /* PCIe Ports */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) #define SB_PCIE_DEV 0x15 #define SB_PCIE_PORT1_FUNC 0 #define SB_PCIE_PORT2_FUNC 1 diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c index 4ca29e08c5..8a07565c9a 100644 --- a/src/southbridge/amd/agesa/hudson/resume.c +++ b/src/southbridge/amd/agesa/hudson/resume.c @@ -104,7 +104,7 @@ static void s3_resume_init_data(FCH_DATA_BLOCK *FchParams) FchParams->Usb.Ohci4Enable = FchInterfaceDefault.Ohci4Enable; FchParams->HwAcpi.PwrFailShadow = FchInterfaceDefault.FchPowerFail; - FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchParams->Usb.Xhci1Enable = FALSE; #if DUMP_FCH_SETTING diff --git a/src/southbridge/amd/agesa/hudson/sata.c b/src/southbridge/amd/agesa/hudson/sata.c index b08e298f06..75ec43997e 100644 --- a/src/southbridge/amd/agesa/hudson/sata.c +++ b/src/southbridge/amd/agesa/hudson/sata.c @@ -23,7 +23,7 @@ static void sata_init(struct device *dev) { -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) /************************************** * Configure the SATA port multiplier * **************************************/ diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index a1c0755da0..76c587779a 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -36,7 +36,7 @@ #define SPI_REG_CNTRL11 0xd #define CNTRL11_FIFOPTR_MASK 0x07 -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) #define AMD_SB_SPI_TX_LEN 64 #else #define AMD_SB_SPI_TX_LEN 8 @@ -110,7 +110,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, readoffby1 = bytesout ? 0 : 1; -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) spi_write(0x1E, 5); spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ spi_write(0x1E, 6); @@ -144,7 +144,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, int chipset_volatile_group_begin(const struct spi_flash *flash) { - if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM)) + if (!CONFIG(HUDSON_IMC_FWM)) return 0; ImcSleep(NULL); @@ -153,7 +153,7 @@ int chipset_volatile_group_begin(const struct spi_flash *flash) int chipset_volatile_group_end(const struct spi_flash *flash) { - if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM)) + if (!CONFIG(HUDSON_IMC_FWM)) return 0; ImcWakeup(NULL); -- cgit v1.2.3