From 2093c4f7c220068e630b756dd19b89ab1ddec88e Mon Sep 17 00:00:00 2001
From: Dave Frodin <dave.frodin@se-eng.com>
Date: Fri, 13 Jun 2014 08:12:48 -0600
Subject: AMD/agesa: Add functions for AMD PCI IRQ routing
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Port the changes that were made in amd/cimx to amd/agesa
as were done in:
   commit c93a75a5ab067f86104028b74d92fc54cb939cd5
   Author: Mike Loptien <mike.loptien@se-eng.com>
   Date:   Fri Jun 6 15:16:29 2014 -0600

      AMD/CIMx: Add functions for AMD PCI IRQ routing

This change also moves the PCI INT functions to
southbridge/amd so that they can be used by CIMX and
AGESA. The amd/persimmon board is updated for this
change.

Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Change-Id: I525be90f9cf8e825e162d53a7ecd1e69c6e27637
Reviewed-on: http://review.coreboot.org/6065
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
 src/southbridge/amd/agesa/hudson/pci.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

(limited to 'src/southbridge/amd/agesa/hudson/pci.c')

diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c
index 58498f4ab6..e8836e4c7d 100644
--- a/src/southbridge/amd/agesa/hudson/pci.c
+++ b/src/southbridge/amd/agesa/hudson/pci.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -23,11 +24,35 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include "hudson.h"
+#include <southbridge/amd/amd_pci_util.h>
+#include <bootstate.h>
 
 static void pci_init(struct device *dev)
 {
 }
 
+/*
+ * Update the PCI devices with a valid IRQ number
+ * that is set in the mainboard PCI_IRQ structures.
+ */
+static void set_pci_irqs(void *unused)
+{
+	/* Write PCI_INTR regs 0xC00/0xC01 */
+	write_pci_int_table();
+
+	/* Write IRQs for all devicetree enabled devices */
+	write_pci_cfg_irqs();
+}
+
+/*
+ * Hook this function into the PCI state machine
+ * on entry into BS_DEV_ENABLE.
+ */
+BOOT_STATE_INIT_ENTRIES(pci_irq_update) = {
+	BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY,
+	                      set_pci_irqs, NULL),
+};
+
 static struct pci_operations lops_pci = {
 	.set_subsystem = 0,
 };
-- 
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