From ac1b875b554f45b0c98d375369119495b7ad2a2a Mon Sep 17 00:00:00 2001 From: Dave Frodin Date: Thu, 5 Jun 2014 14:30:22 -0600 Subject: amd/southbridge/lpc: SPI BAR has fixed size/location MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The CIMX sb700/sb800/sb900 and agesa/hudson code was treating the LPC SPI BAR as a normal PCI BAR. This will set the resources for a fixed size at a fixed address. This was tested on hp/abm, amd/persimmon, and gizmosphere/gizmo boards. Change-Id: I1367efe0bbb53b7727258585963f61f4bd02ea1d Signed-off-by: Dave Frodin Reviewed-on: http://review.coreboot.org/5947 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/southbridge/amd/agesa/hudson/lpc.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'src/southbridge/amd/agesa/hudson/lpc.c') diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 71aaf6fe91..c8051ec42d 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -87,8 +87,6 @@ static void hudson_lpc_read_resources(device_t dev) /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ - pci_get_resource(dev, 0xA0); /* SPI ROM base address */ - /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res->base = 0; @@ -102,6 +100,9 @@ static void hudson_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + /* Add a memory resource for the SPI BAR. */ + fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE); + res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; @@ -115,12 +116,10 @@ static void hudson_lpc_set_resources(struct device *dev) struct resource *res; /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ - res = find_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); - res->base |= PCI_COMMAND_MEMORY; + res = find_resource(dev, 2); + pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE); pci_dev_set_resources(dev); - - } /** -- cgit v1.2.3