From 1b1b795f97d2aaa2c6104f164ed2b4e792895019 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sun, 9 Nov 2014 14:54:06 +0200 Subject: AGESA: Remove redundant Avalon support from Hudson MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avalon support now lives under pi/avalon so we can restore Hudson to the state before it was added there. Change-Id: Id96973f3458fae162232c160e602595b58c43027 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/7389 Reviewed-by: Edward O'Callaghan Tested-by: build bot (Jenkins) --- src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h') diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h index f66547158d..01f769c46d 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h @@ -29,8 +29,6 @@ #define FCH_INT_TABLE_SIZE 0x54 #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) #define FCH_INT_TABLE_SIZE 0x42 -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON) -#define FCH_INT_TABLE_SIZE 0x63 #endif #define PIRQ_NC 0x1F /* Not Used */ @@ -75,10 +73,6 @@ #define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ #define PIRQ_IDE 0x40 /* IDE 14h.1 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON) -#define PIRQ_SD 0x17 /* SD */ -#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ -#endif #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define PIRQ_SD 0x42 /* SD 14h.7 */ #define PIRQ_GPP0 0x50 /* GPP INT 0 */ -- cgit v1.2.3