From f97232236891bc8f5c816a96c98807a0f2449234 Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Tue, 28 May 2019 10:37:24 +0200 Subject: src/soc/intel/common/smbios: Add addtional infos to dimm_info Add ECC Support and VDD Voltage to dimm_info struct. Now Bus Width and ECCSupport will be propagated correctly in SMBIOS Type 17 Entry. Change-Id: Ic6f0d4b223f1490ec7aa71a6105603635b514021 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/33031 Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/meminit_util_apl.c | 4 +++- src/soc/intel/apollolake/meminit_util_glk.c | 4 +++- src/soc/intel/cannonlake/romstage/romstage.c | 6 +++++- src/soc/intel/common/smbios.c | 12 +++++++++++- src/soc/intel/common/smbios.h | 3 ++- src/soc/intel/icelake/romstage/romstage.c | 6 +++++- src/soc/intel/skylake/romstage/romstage_fsp20.c | 5 ++++- 7 files changed, 33 insertions(+), 7 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/apollolake/meminit_util_apl.c b/src/soc/intel/apollolake/meminit_util_apl.c index b272a99efe..16d14d945f 100644 --- a/src/soc/intel/apollolake/meminit_util_apl.c +++ b/src/soc/intel/apollolake/meminit_util_apl.c @@ -91,7 +91,9 @@ void save_lpddr4_dimm_info_part_num(const char *dram_part_num) dram_part_num, strlen(dram_part_num), NULL, /* SPD not available */ - memory_info_hob->DataWidth); + memory_info_hob->DataWidth, + 0, + 0); index++; } } diff --git a/src/soc/intel/apollolake/meminit_util_glk.c b/src/soc/intel/apollolake/meminit_util_glk.c index 29dcd56767..59e133076a 100644 --- a/src/soc/intel/apollolake/meminit_util_glk.c +++ b/src/soc/intel/apollolake/meminit_util_glk.c @@ -97,7 +97,9 @@ void save_lpddr4_dimm_info_part_num(const char *dram_part_num) dram_part_num, strlen(dram_part_num), src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, - memory_info_hob->DataWidth); + memory_info_hob->DataWidth, + 0, + 0); index++; } } diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 98d4c006a8..fa530a29a6 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -101,6 +101,8 @@ static void save_dimm_info(void) mainboard_get_dram_part_num(&dram_part_num, &dram_part_num_len); + u8 memProfNum = memory_info_hob->MemoryProfile; + /* Populate the DIMM information */ dimm_info_fill(dest_dimm, src_dimm->DimmCapacity, @@ -112,7 +114,9 @@ static void save_dimm_info(void) dram_part_num, dram_part_num_len, src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, - memory_info_hob->DataWidth); + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport); index++; } } diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index d89e9d5827..e3ed3a2e69 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -22,7 +22,8 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, - const u8 *module_serial_num, u16 data_width) + const u8 *module_serial_num, u16 data_width, u32 vdd_voltage, + bool ecc_support) { dimm->dimm_size = dimm_capacity; dimm->ddr_type = ddr_type; @@ -30,6 +31,12 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, dimm->rank_per_dimm = rank_per_dimm; dimm->channel_num = channel_id; dimm->dimm_num = dimm_id; + if (vdd_voltage > 0xFFFF) { + dimm->vdd_voltage = 0xFFFF; + } else { + dimm->vdd_voltage = vdd_voltage; + } + strncpy((char *)dimm->module_part_number, module_part_num, min(sizeof(dimm->module_part_number), @@ -57,4 +64,7 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, printk(BIOS_NOTICE, "Incorrect DIMM Data width: %u\n", (unsigned int)data_width); } + + if (ecc_support) + dimm->bus_width |= 0x8; } diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h index 5824f5d665..12b8da0d85 100644 --- a/src/soc/intel/common/smbios.h +++ b/src/soc/intel/common/smbios.h @@ -26,6 +26,7 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, - const u8 *module_serial_num, u16 data_width); + const u8 *module_serial_num, u16 data_width, u32 vdd_voltage, + bool ecc_support); #endif /* _COMMON_SMBIOS_H_ */ diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 179d99cff6..a09641cf44 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -86,6 +86,8 @@ static void save_dimm_info(void) if (src_dimm->Status != DIMM_PRESENT) continue; + u8 memProfNum = memory_info_hob->MemoryProfile; + /* Populate the DIMM information */ dimm_info_fill(dest_dimm, src_dimm->DimmCapacity, @@ -97,7 +99,9 @@ static void save_dimm_info(void) (const char *)src_dimm->ModulePartNum, sizeof(src_dimm->ModulePartNum), src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, - memory_info_hob->DataWidth); + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport); index++; } } diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 04c369beb8..2819c6f260 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -114,6 +114,7 @@ static void save_dimm_info(void) ddr_type = MEMORY_TYPE_UNKNOWN; break; } + u8 memProfNum = memory_info_hob->MemoryProfile; /* Populate the DIMM information */ dimm_info_fill(dest_dimm, @@ -126,7 +127,9 @@ static void save_dimm_info(void) (const char *)src_dimm->ModulePartNum, sizeof(src_dimm->ModulePartNum), src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, - memory_info_hob->DataWidth); + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport); index++; } } -- cgit v1.2.3