From f8744425537f09738a153c8368364070be559f20 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 18 Apr 2018 16:32:30 -0600 Subject: soc/intel/common: disable paging if PAGING_IN_CACHE_AS_RAM enabled When tearing down cache-as-ram disable paging if PAGING_IN_CACHE_AS_RAM is enabled. BUG=b:72728953 Change-Id: I86e8a57a1187876dcbedce9f4f6b05be30aea7c6 Signed-off-by: Aaron Durbin Signed-off-by: Naresh G Solanki Signed-off-by: Hannah Williams Reviewed-on: https://review.coreboot.org/25732 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/cpu/car/exit_car.S | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index 15e7f17358..86feddca43 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -22,6 +22,21 @@ .global chipset_teardown_car chipset_teardown_car: +#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM) + /* + * Since Page table is located in CAR, disable paging before CAR + * teardown. Also clear CR3 and CR4.PAE. + */ + mov %cr0, %eax + and $(~(CR0_PG)), %eax + mov %eax, %cr0 + xor %eax, %eax + mov %eax, %cr3 + mov %cr4, %eax + and $(~(CR4_PAE)), %eax + mov %eax, %cr4 +#endif + /* * Retrieve return address from stack as it will get trashed below if * execution is utilizing the cache-as-ram stack. -- cgit v1.2.3