From f5e94b6e7283794bad7a0c527c6c75dc92d6f460 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Tue, 8 Mar 2022 23:39:20 +0530 Subject: soc/intel/alderlake: Enable debug driver for Alder Lake platform The patch enables dynamic debug capability driver for Alder Lake platform. BUG=b:153410586 TEST= Build code for Brya Signed-off-by: Sridhar Siricilla Change-Id: Ic4df3d7f3d6585bd37c632b1a3f0a47c94b63697 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62652 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi Reviewed-by: Subrata Banik --- src/soc/intel/alderlake/Kconfig | 1 + src/soc/intel/alderlake/romstage/romstage.c | 4 ++++ 2 files changed, 5 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 3570f27578..6b0a27a47b 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -98,6 +98,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_USB4_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG + select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 5e79535ecf..3f29fc30b9 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -134,6 +135,9 @@ void mainboard_romstage_entry(void) /* Initialize HECI interface */ heci_init(HECI1_BASE_ADDRESS); + if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE)) + pre_mem_debug_init(); + s3wake = pmc_fill_power_state(ps) == ACPI_S3; if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) { -- cgit v1.2.3