From f41ad02c83b66e72d68801413a15cf869bc97268 Mon Sep 17 00:00:00 2001 From: York Yang Date: Wed, 14 Oct 2015 07:00:30 -0700 Subject: intel/fsp_baytrail: Load BSP microcode in bootblock Load microcode to BSP in bootblock so later on the FSP TempRamInit call can be success. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load. If BSP is not loaded a microcode before calling TempRamInit API, the call will fail with the error No Valid Microcode Was Found. Change-Id: I1fbe68e14e5a24d8f2da70603cd2f03675b9ca81 Signed-off-by: York Yang Reviewed-on: http://review.coreboot.org/11896 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Martin Roth --- src/soc/intel/fsp_baytrail/bootblock/bootblock.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/soc') diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c index 9c131d26be..bba5cf497c 100644 --- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c +++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -112,9 +113,11 @@ static void set_up_lpc_pads(void) static void bootblock_cpu_init(void) { - check_for_warm_reset(); + /* Load microcode before any caching. */ + intel_update_microcode_from_cbfs(); + /* Allow memory-mapped PCI config access. */ setup_mmconfig(); enable_rom_caching(); -- cgit v1.2.3