From f32d1e3acbff0180e608f8965073c10b26cf626f Mon Sep 17 00:00:00 2001 From: Mandy Liu Date: Tue, 11 Oct 2022 13:56:27 +0800 Subject: soc/mediatek/mt8186: Enable ADSP clock To use SOF correctly, we need to enable ADSP clock. TEST=SOF driver is functional. BUG=b:204229221 Signed-off-by: Mandy Liu Change-Id: Ia17db889829df2668cf2af1b71c6468230de68e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68287 Reviewed-by: Yidi Lin Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8186/pll.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'src/soc') diff --git a/src/soc/mediatek/mt8186/pll.c b/src/soc/mediatek/mt8186/pll.c index 7179c2eac6..9d8343b7ef 100644 --- a/src/soc/mediatek/mt8186/pll.c +++ b/src/soc/mediatek/mt8186/pll.c @@ -474,8 +474,11 @@ void mt_pll_init(void) write32(&mt8186_infracfg_ao->module_sw_cg_0_clr, 0x00000030); /* [7] DVFSRC_CG, [20] DEVICE_APC_CG */ write32(&mt8186_infracfg_ao->module_sw_cg_1_clr, 0x00100080); - /* [15] SEJ_F13M_CK_CG, [16] AES_TOP0_BCLK_CK_CG */ - write32(&mt8186_infracfg_ao->module_sw_cg_3_clr, 0x00018000); + /* + * [15] SEJ_F13M_CK_CG, [16] AES_TOP0_BCLK_CK_CG, + * [22] FADSP_26M_CG, [23] FADSP_32K_CG, [27] FADSP_CK_CG + */ + write32(&mt8186_infracfg_ao->module_sw_cg_3_clr, 0x08C18000); } void mt_pll_raise_little_cpu_freq(u32 freq) -- cgit v1.2.3