From f26a1985bf2d5bea1b345cd306443e0ebb77e27a Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Wed, 2 Oct 2019 10:16:26 +0200 Subject: soc/intel/braswell/chip.h: Add IGD_MEMSIZE_xxMB Add defines to have some more readable code for devcietree.cb. BUG=N/A TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701 Change-Id: Ifc1a7657a528d1fc570dd16df66b078e37e014cb Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/35751 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/soc/intel/braswell/chip.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 747b941f55..9f790dc140 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -32,6 +32,11 @@ #define SVID_CONFIG3 3 #define SVID_PMIC_CONFIG 8 +#define IGD_MEMSIZE_32MB 0x01 +#define IGD_MEMSIZE_64MB 0x02 +#define IGD_MEMSIZE_96MB 0x03 +#define IGD_MEMSIZE_128MB 0x04 + enum lpe_clk_src { LPE_CLK_SRC_XTAL, LPE_CLK_SRC_PLL, -- cgit v1.2.3