From f167df4d3fbfd74b4bbf35502daf8e533a925eaf Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 27 May 2023 00:00:53 +0200 Subject: soc/amd/picasso/acpi/sb_pci0_fch: replace Memory32Fixed with DWordMemory This brings the ACPI code more in line with both what the new code for the AMD SoCs will do and also what the current Intel code does. This was mainly done to have a reduced delta to the new AMD domain resource handling functions to debug it, but it might still be useful to upstream this change. Signed-off-by: Felix Held Change-Id: I8cca05976b1c9d4e994e407b8c0197da7dd35eb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75487 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Martin Roth --- src/soc/amd/picasso/acpi/sb_pci0_fch.asl | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index df21e9d9a5..1f2c0d9310 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -59,23 +59,33 @@ Name(CRES, ResourceTemplate() { 0xf300 /* length */ ) - Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadOnly, + 0x00000000, 0x000c0000, 0x000dffff, 0x00000000, + 0x00020000) /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM01) }) /* End Name(_SB.PCI0.CRES) */ Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* Find PCI resource area in CRES */ + CreateDwordField (CRES, ^PM01._MIN, P1MN) + CreateDwordField (CRES, ^PM01._MAX, P1MX) + CreateDwordField (CRES, ^PM01._LEN, P1LN) /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */ - MM1B = TOM1 - Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS - Local0 -= TOM1 - MM1L = Local0 + P1MN = TOM1 + P1MX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1 + P1LN = P1MX - P1MN + 1 CreateWordField(CRES, ^PSB0._MAX, BMAX) CreateWordField(CRES, ^PSB0._LEN, BLEN) -- cgit v1.2.3