From ee735945754180544c8bd060d6fc0b9b2c507360 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 7 Sep 2020 17:52:23 +0530 Subject: vendorcode/intel/fsp/fsp2_0/adl: Add FSP header file version 1332 List of changes: 1. Select FSP_HEADER_PATH 2. Select FSP_FD_PATH 3. Select PLATFORM_USES_FSP2_2 4. Select UDK_202005_BINDING Change-Id: Ic5b09bad3c23b84c6ff6b1ea9e1dc684d7463c27 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/45148 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons Reviewed-by: Maulik V Vaghela --- src/soc/intel/alderlake/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index ee1e871ebb..b873a03de8 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -14,6 +14,7 @@ config CPU_SPECIFIC_OPTIONS select IDT_IN_EVERY_STAGE select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED select MICROCODE_BLOB_UNDISCLOSED + select PLATFORM_USES_FSP2_2 select SOC_INTEL_COMMON select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU @@ -26,6 +27,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER select UDELAY_TSC + select UDK_202005_BINDING config DCACHE_RAM_BASE default 0xfef00000 @@ -129,4 +131,12 @@ config CBFS_SIZE config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x1400 +config FSP_HEADER_PATH + string "Location of FSP headers" + default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd" endif -- cgit v1.2.3