From ee2e936f4059d8aad4161d44915a05271df1aaae Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 28 Dec 2018 16:06:45 +0200 Subject: arch/x86: Unify bootblock MMX register usage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Have same usage of registers with romcc bootblock and C_ENVIRONMENT_BOOTBLOCK. Change-Id: Ibfa80e40f0b736a904abf4245fc23efc0cdc458d Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/30490 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/soc/intel/baytrail/romstage/cache_as_ram.inc | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index 945b56d160..8602237d28 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -36,9 +36,6 @@ #define NoEvictMod_MSR 0x2e0 #define BBL_CR_CTL3_MSR 0x11e - /* Save the BIST result. */ - movl %eax, %ebp - cache_as_ram: post_code(0x20) @@ -183,14 +180,13 @@ addrsize_set_high: movl %eax, %esp /* Push the initial TSC value from boot block. The low 32 bits are - * in mm0, and the high 32 bits are in mm1. */ - movd %mm1, %eax + * in mm1, and the high 32 bits are in mm2. */ + movd %mm2, %eax pushl %eax - movd %mm0, %eax + movd %mm1, %eax pushl %eax /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp + movd %mm0, %eax pushl %eax before_romstage: -- cgit v1.2.3