From ed6c99990439b51a7b3b03dd5d4d122b69ddbc58 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 7 Jun 2023 20:50:08 +0200 Subject: soc/amd: add ops xhci_pci_ops to XHCI controllers in devicetree Instead of adding the new PCI IDs of the XHCI controllers in every new chip generation to the pci_xhci driver, bind the driver to the internal PCI devices of the XHCI controllers via the device ops statement in the chipset devicetree. The PCI device function of the XHCI2 controller in Mendocino can be either a dummy device or the XHCI controller, so the device ops are attached to that device in the mainboard devicetree instead. The Glinda code is right now just a copy of the Mendocino code, so it'll change in the future, but for consistency the equivalent changes to those in Mendocino are applied there too. Since the device ops are now attached to the devices via the static devicetree entry, also remove both the xhci_pci_driver struct and the amd_pci_device_ids array from drivers/usb/pci_xhci/pci_xhci.c. TEST=SSDT entries for the XHCI controllers are still generated on Mandolin. Signed-off-by: Felix Held Change-Id: I9c455002c6d2aac576fe24eee0c31744b4507bb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75713 Tested-by: build bot (Jenkins) Reviewed-by: Jon Murphy Reviewed-by: Fred Reitberger Reviewed-by: Eric Lai --- src/soc/amd/cezanne/chipset.cb | 2 ++ src/soc/amd/glinda/chipset.cb | 3 +++ src/soc/amd/mendocino/chipset_mendocino.cb | 3 +++ src/soc/amd/mendocino/chipset_rembrandt.cb | 3 +++ src/soc/amd/picasso/chipset.cb | 8 ++++++-- 5 files changed, 17 insertions(+), 2 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index c7793905ae..0762ea1d26 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -28,6 +28,7 @@ chip soc/amd/cezanne device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor device pci 0.3 alias xhci_0 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_0_root_hub off @@ -53,6 +54,7 @@ chip soc/amd/cezanne end end device pci 0.4 alias xhci_1 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_1_root_hub off diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb index ad477c7c90..bf7d67d81b 100644 --- a/src/soc/amd/glinda/chipset.cb +++ b/src/soc/amd/glinda/chipset.cb @@ -26,6 +26,7 @@ chip soc/amd/glinda device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor device pci 0.3 alias xhci_0 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_0_root_hub off @@ -42,6 +43,7 @@ chip soc/amd/glinda end end device pci 0.4 alias xhci_1 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_1_root_hub off @@ -71,6 +73,7 @@ chip soc/amd/glinda device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C ops amd_internal_pcie_gpp_ops device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID + # When using this as XHCI2, the mainboard devicetree needs to add ops xhci_pci_ops end device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index 691cca03d9..e40124f6ff 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -22,6 +22,7 @@ chip soc/amd/mendocino device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor device pci 0.3 alias xhci_0 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_0_root_hub off @@ -38,6 +39,7 @@ chip soc/amd/mendocino end end device pci 0.4 alias xhci_1 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_1_root_hub off @@ -66,6 +68,7 @@ chip soc/amd/mendocino device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C ops amd_internal_pcie_gpp_ops device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID + # When using this as XHCI2, the mainboard devicetree needs to add ops xhci_pci_ops end device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index fd31efeb8e..394f057bfa 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -24,6 +24,7 @@ chip soc/amd/mendocino device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor device pci 0.3 alias xhci_0 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_0_root_hub off @@ -40,6 +41,7 @@ chip soc/amd/mendocino end end device pci 0.4 alias xhci_1 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_1_root_hub off @@ -69,6 +71,7 @@ chip soc/amd/mendocino device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C ops amd_internal_pcie_gpp_ops device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID + # When using this as XHCI2, the mainboard devicetree needs to add ops xhci_pci_ops end device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function diff --git a/src/soc/amd/picasso/chipset.cb b/src/soc/amd/picasso/chipset.cb index 6d6177f4b9..bf2c879a23 100644 --- a/src/soc/amd/picasso/chipset.cb +++ b/src/soc/amd/picasso/chipset.cb @@ -22,8 +22,12 @@ chip soc/amd/picasso device pci 0.0 alias gfx off ops amd_graphics_ops end # internal GPU device pci 0.1 alias gfx_hda off end # display HD Audio controller device pci 0.2 alias crypto off end # cryptography coprocessor - device pci 0.3 alias xhci_0 off end - device pci 0.4 alias xhci_1 off end + device pci 0.3 alias xhci_0 off + ops xhci_pci_ops + end + device pci 0.4 alias xhci_1 off + ops xhci_pci_ops + end device pci 0.5 alias acp off ops amd_acp_ops end # audio co-processor device pci 0.6 alias hda off end # main HD Audio Controller device pci 0.7 alias mp2 off end # sensor fusion hub (MP2) -- cgit v1.2.3