From ea4bda55d62d90e008a5aa455f24adcd7759b37a Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Wed, 23 Oct 2019 16:51:26 +0800 Subject: soc/mediatek/mt8183: Add udelay after setting voltages The SOC DRAM team suggested to delay at least 1us after setting new voltage in PMIC wrapper so the new value can be effective. BRANCH=kukui BUG=b:142358843 TEST=emerge-kukui coreboot Change-Id: I19d236769c3c0c87513ea4a0a3f64b83e3a844c2 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/36254 Reviewed-by: Julius Werner Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8183/mt6358.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc') diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index cee9ef2239..4ab0e7ed76 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -874,6 +874,7 @@ void pmic_set_vcore_vol(unsigned int vcore_uv) pwrap_write_field(PMIC_VCORE_OP_EN, 1, 0x7F, 0); pwrap_write_field(PMIC_VCORE_VOSEL, vol_reg, 0x7F, 0); + udelay(1); } unsigned int pmic_get_vdram1_vol(void) @@ -895,6 +896,7 @@ void pmic_set_vdram1_vol(unsigned int vdram_uv) pwrap_write_field(PMIC_VDRAM1_OP_EN, 1, 0x7F, 0); pwrap_write_field(PMIC_VDRAM1_VOSEL, vol_reg, 0x7F, 0); + udelay(1); } unsigned int pmic_get_vddq_vol(void) -- cgit v1.2.3