From e80a1b1690d9d70e14cd7aa0b99fa317ac33b4e4 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 5 Jun 2020 09:51:30 -0600 Subject: soc/amd/picasso: remove save/restore MTRRs around FSP-M AGESA FSP-M implementation is now not updating MTRRs out from under the caller. As such, remove the save/restore of MTRRs from the FSP-M call. BUG=b:155426691 Change-Id: I14f3b18dd373ce17957ef3857920e1c4e2901bbe Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/42104 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Furquan Shaikh Reviewed-by: Felix Held --- src/soc/amd/picasso/Makefile.inc | 1 - src/soc/amd/picasso/include/soc/mtrr.h | 9 --- src/soc/amd/picasso/mtrr.c | 111 --------------------------------- src/soc/amd/picasso/romstage.c | 19 +----- 4 files changed, 1 insertion(+), 139 deletions(-) delete mode 100644 src/soc/amd/picasso/include/soc/mtrr.h delete mode 100644 src/soc/amd/picasso/mtrr.c (limited to 'src/soc') diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 5744c63cb8..3b59684f18 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -30,7 +30,6 @@ romstage-y += tsc_freq.c romstage-y += southbridge.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += psp.c -romstage-y += mtrr.c romstage-y += config.c verstage-y += gpio.c diff --git a/src/soc/amd/picasso/include/soc/mtrr.h b/src/soc/amd/picasso/include/soc/mtrr.h deleted file mode 100644 index 8746e184ea..0000000000 --- a/src/soc/amd/picasso/include/soc/mtrr.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __PICASSO_MTRR_H__ -#define __PICASSO_MTRR_H__ - -void picasso_save_mtrrs(void); -void picasso_restore_mtrrs(void); - -#endif /* __PICASSO_MTRR_H__ */ diff --git a/src/soc/amd/picasso/mtrr.c b/src/soc/amd/picasso/mtrr.c deleted file mode 100644 index d2f8ff32b8..0000000000 --- a/src/soc/amd/picasso/mtrr.c +++ /dev/null @@ -1,111 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include - -/* Picasso defines 8 Variable MTRRs */ -#define MAX_VARIABLE_MTRRS 8 -#define SYS_CFG_MTRR_BITS ( \ -SYSCFG_MSR_TOM2WB | \ -SYSCFG_MSR_TOM2En | \ -SYSCFG_MSR_MtrrVarDramEn | \ -SYSCFG_MSR_MtrrFixDramModEn | \ -SYSCFG_MSR_MtrrFixDramEn \ -) - -static const unsigned int fixed_mtrr_offsets[] = { - MTRR_FIX_64K_00000, - MTRR_FIX_16K_80000, - MTRR_FIX_16K_A0000, - MTRR_FIX_4K_C0000, - MTRR_FIX_4K_C8000, - MTRR_FIX_4K_D0000, - MTRR_FIX_4K_D8000, - MTRR_FIX_4K_E0000, - MTRR_FIX_4K_E8000, - MTRR_FIX_4K_F0000, - MTRR_FIX_4K_F8000, -}; - -static int mtrrs_saved; -static msr_t sys_cfg; -static msr_t mtrr_def; -static msr_t mtrr_base[MAX_VARIABLE_MTRRS]; -static msr_t mtrr_mask[MAX_VARIABLE_MTRRS]; -static msr_t fixed_mtrrs[ARRAY_SIZE(fixed_mtrr_offsets)]; - -void picasso_save_mtrrs(void) -{ - unsigned int i; - int mtrrs; - - mtrrs = get_var_mtrr_count(); - - ASSERT_MSG(mtrrs == MAX_VARIABLE_MTRRS, "Unexpected number of MTRRs\n"); - - for (i = 0; i < MAX_VARIABLE_MTRRS; ++i) { - mtrr_base[i] = rdmsr(MTRR_PHYS_BASE(i)); - mtrr_mask[i] = rdmsr(MTRR_PHYS_MASK(i)); - printk(BIOS_DEBUG, - "Saving Variable MTRR %d: Base: 0x%08x 0x%08x, Mask: 0x%08x 0x%08x\n", i, - mtrr_base[i].hi, mtrr_base[i].lo, mtrr_mask[i].hi, mtrr_mask[i].lo); - } - - for (i = 0; i < ARRAY_SIZE(fixed_mtrr_offsets); ++i) { - fixed_mtrrs[i] = rdmsr(fixed_mtrr_offsets[i]); - printk(BIOS_DEBUG, "Saving Fixed MTRR %u: 0x%08x 0x%08x\n", i, - fixed_mtrrs[i].hi, fixed_mtrrs[i].lo); - } - - mtrr_def = rdmsr(MTRR_DEF_TYPE_MSR); - printk(BIOS_DEBUG, "Saving Default Type MTRR: 0x%08x 0x%08x\n", mtrr_def.hi, - mtrr_def.lo); - - sys_cfg = rdmsr(SYSCFG_MSR); - printk(BIOS_DEBUG, "Saving SYS_CFG: 0x%08x 0x%08x\n", mtrr_def.hi, mtrr_def.lo); - - mtrrs_saved = 1; -} - -static void update_if_changed(unsigned int offset, msr_t expected) -{ - msr_t tmp = rdmsr(offset); - if (tmp.lo == expected.lo && tmp.hi == expected.hi) - return; - - printk(BIOS_INFO, "MSR %#x was modified: 0x%08x 0x%08x\n", offset, tmp.hi, tmp.lo); - wrmsr(offset, expected); -} - -void picasso_restore_mtrrs(void) -{ - unsigned int i; - msr_t tmp_sys_cfg; - - ASSERT_MSG(mtrrs_saved, "Must save MTRRs before restoring.\n"); - - for (i = 0; i < MAX_VARIABLE_MTRRS; ++i) { - update_if_changed(MTRR_PHYS_BASE(i), mtrr_base[i]); - update_if_changed(MTRR_PHYS_MASK(i), mtrr_mask[i]); - } - - for (i = 0; i < ARRAY_SIZE(fixed_mtrr_offsets); ++i) - update_if_changed(fixed_mtrr_offsets[i], fixed_mtrrs[i]); - - update_if_changed(MTRR_DEF_TYPE_MSR, mtrr_def); - - tmp_sys_cfg = rdmsr(SYSCFG_MSR); - - /* We only care about the MTRR bits in the SYSCFG register */ - if ((tmp_sys_cfg.lo & SYS_CFG_MTRR_BITS) != (sys_cfg.lo & SYS_CFG_MTRR_BITS)) { - printk(BIOS_INFO, "SYS_CFG was modified: 0x%08x 0x%08x\n", tmp_sys_cfg.hi, - tmp_sys_cfg.lo); - tmp_sys_cfg.lo &= ~SYS_CFG_MTRR_BITS; - tmp_sys_cfg.lo |= (sys_cfg.lo & SYS_CFG_MTRR_BITS); - wrmsr(SYSCFG_MSR, tmp_sys_cfg); - } -} diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 0bbceec0d1..35d2aa2b46 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include "chip.h" #include @@ -22,16 +21,6 @@ void __weak mainboard_romstage_entry_s3(int s3_resume) /* By default, don't do anything */ } -/* TODO(b/155426691): Make FSP AGESA leave MTRRs alone */ -static void clear_agesa_mtrrs(void) -{ - disable_cache(); - - picasso_restore_mtrrs(); - - enable_cache(); -} - void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *mcfg = &mupd->FspmConfig; @@ -95,15 +84,9 @@ asmlinkage void car_stage_entry(void) printk(BIOS_DEBUG, "Family_Model: %08x\n", val); post_code(0x43); - picasso_save_mtrrs(); - - post_code(0x44); fsp_memory_init(s3_resume); - post_code(0x45); - clear_agesa_mtrrs(); - - post_code(0x46); + post_code(0x44); run_ramstage(); post_code(0x50); /* Should never see this post code. */ -- cgit v1.2.3