From e7377556cc33b10fdba6d956ac83d823478f5eb4 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 21 Jun 2018 16:20:55 +0300 Subject: device: Use pcidev_path_on_root() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/30400 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/common/block/pi/agesawrapper.c | 2 +- src/soc/amd/stoneyridge/BiosCallOuts.c | 4 ++-- src/soc/amd/stoneyridge/gpio.c | 2 +- src/soc/amd/stoneyridge/i2c.c | 2 +- src/soc/amd/stoneyridge/romstage.c | 4 ++-- src/soc/amd/stoneyridge/southbridge.c | 8 ++++---- src/soc/intel/common/block/chip/chip.c | 2 +- src/soc/intel/common/block/gspi/gspi.c | 2 +- src/soc/intel/common/block/i2c/i2c.c | 4 ++-- src/soc/intel/fsp_baytrail/acpi.c | 2 +- src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 2 +- src/soc/intel/fsp_broadwell_de/acpi.c | 4 ++-- src/soc/intel/quark/romstage/fsp1_1.c | 2 +- src/soc/intel/quark/romstage/fsp2_0.c | 2 +- 14 files changed, 21 insertions(+), 21 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 9c10fec407..d376e6db41 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -324,7 +324,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void) */ AMD_LATE_PARAMS *LateParams = create_struct(&AmdParamStruct); - const struct device *dev = dev_find_slot(0, IOMMU_DEVFN); + const struct device *dev = pcidev_path_on_root(IOMMU_DEVFN); if (dev && dev->enabled) { LateParams->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1; diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index fdef166c62..018975f098 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -52,7 +52,7 @@ AGESA_STATUS agesa_fch_initenv(uint32_t Func, uintptr_t FchData, void *ConfigPtr) { AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - const struct device *dev = dev_find_slot(0, SATA_DEVFN); + const struct device *dev = pcidev_path_on_root(SATA_DEVFN); if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; @@ -104,7 +104,7 @@ AGESA_STATUS agesa_ReadSpd(uint32_t Func, uintptr_t Data, void *ConfigPtr) if (!ENV_ROMSTAGE) return AGESA_UNSUPPORTED; - dev = dev_find_slot(0, DCT_DEVFN); + dev = pcidev_path_on_root(DCT_DEVFN); if (dev == NULL) return AGESA_ERROR; diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index 3eaa3a03c8..955cc6a0cc 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -347,7 +347,7 @@ static void restore_i2c_pin_registers(uint8_t gpio, void sb_reset_i2c_slaves(void) { const struct soc_amd_stoneyridge_config *cfg; - const struct device *dev = dev_find_slot(0, GNB_DEVFN); + const struct device *dev = pcidev_path_on_root(GNB_DEVFN); struct soc_amd_i2c_save save_table[saved_pins_count]; uint8_t i, j, control; diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index b90e5d7857..45057a0b2e 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -45,7 +45,7 @@ uintptr_t dw_i2c_base_address(unsigned int bus) static const struct soc_amd_stoneyridge_config *get_soc_config(void) { - const struct device *dev = dev_find_slot(0, GNB_DEVFN); + const struct device *dev = pcidev_path_on_root(GNB_DEVFN); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 931448869e..9f8aed8d59 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -187,7 +187,7 @@ asmlinkage void car_stage_entry(void) void SetMemParams(AMD_POST_PARAMS *PostParams) { const struct soc_amd_stoneyridge_config *cfg; - const struct device *dev = dev_find_slot(0, GNB_DEVFN); + const struct device *dev = pcidev_path_on_root(GNB_DEVFN); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n"); @@ -224,7 +224,7 @@ void SetMemParams(AMD_POST_PARAMS *PostParams) void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly) { const struct soc_amd_stoneyridge_config *cfg; - const struct device *dev = dev_find_slot(0, GNB_DEVFN); + const struct device *dev = pcidev_path_on_root(GNB_DEVFN); struct _PLATFORM_CONFIGURATION *platform; if (!dev || !dev->chip_info) { diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index f56123c99b..eb4188219b 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -73,7 +73,7 @@ static inline int sb_ide_enable(void) void SetFchResetParams(FCH_RESET_INTERFACE *params) { - const struct device *dev = dev_find_slot(0, SATA_DEVFN); + const struct device *dev = pcidev_path_on_root(SATA_DEVFN); params->Xhci0Enable = IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE); if (dev && dev->enabled) { params->SataEnable = sb_sata_enable(); @@ -86,7 +86,7 @@ void SetFchResetParams(FCH_RESET_INTERFACE *params) void SetFchEnvParams(FCH_INTERFACE *params) { - const struct device *dev = dev_find_slot(0, SATA_DEVFN); + const struct device *dev = pcidev_path_on_root(SATA_DEVFN); params->AzaliaController = AzEnable; params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE; if (dev && dev->enabled) { @@ -904,9 +904,9 @@ static void set_sb_final_nvs(void) gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB2); gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3); /* Rely on these being in sync with devicetree */ - sd = dev_find_slot(0, SD_DEVFN); + sd = pcidev_path_on_root(SD_DEVFN); gnvs->aoac.st_e = sd && sd->enabled ? 1 : 0; - sata = dev_find_slot(0, SATA_DEVFN); + sata = pcidev_path_on_root(SATA_DEVFN); gnvs->aoac.sd_e = sata && sata->enabled ? 1 : 0; gnvs->aoac.espi = 1; diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c index aecf060e3f..3dae6214ff 100644 --- a/src/soc/intel/common/block/chip/chip.c +++ b/src/soc/intel/common/block/chip/chip.c @@ -22,7 +22,7 @@ const struct soc_intel_common_config *chip_get_common_soc_structure(void) const struct soc_intel_common_config *soc_config; const config_t *config; int devfn = SA_DEVFN_ROOT; - const struct device *dev = dev_find_slot(0, devfn); + const struct device *dev = pcidev_path_on_root(devfn); if (!dev || !dev->chip_info) die("Could not find SA_DEV_ROOT devicetree config!\n"); diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index d4cb9f20ff..445da363b9 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -236,7 +236,7 @@ static uintptr_t gspi_calc_base_addr(unsigned int gspi_bus) if (devfn < 0) return 0; - dev = dev_find_slot(0, devfn); + dev = pcidev_path_on_root(devfn); if (!dev || !dev->enabled) return 0; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 01a9bc3ff7..f72adfce8a 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -65,7 +65,7 @@ static int lpss_i2c_early_init_bus(unsigned int bus) /* Look up the controller device in the devicetree */ dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - tree_dev = dev_find_slot(0, devfn); + tree_dev = pcidev_path_on_root(devfn); if (!tree_dev || !tree_dev->enabled) { printk(BIOS_ERR, "I2C%u device not enabled\n", bus); return -1; @@ -134,7 +134,7 @@ uintptr_t dw_i2c_base_address(unsigned int bus) return (uintptr_t)NULL; /* devfn -> dev */ - dev = dev_find_slot(0, devfn); + dev = pcidev_path_on_root(devfn); if (!dev || !dev->enabled) return (uintptr_t)NULL; diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index f3436c0031..55e4a86f9b 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -173,7 +173,7 @@ typedef struct soc_intel_fsp_baytrail_config config_t; void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - struct device *lpcdev = dev_find_slot(0, FADT_SOC_LPC_DEVFN); + struct device *lpcdev = pcidev_path_on_root(FADT_SOC_LPC_DEVFN); u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; config_t *config = lpcdev->chip_info; diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index 13bc883781..3786c0cc35 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -86,7 +86,7 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U DEVTREE_CONST config_t *config; printk(FSP_INFO_LEVEL, "Configure Default UPD Data\n"); - dev = dev_find_slot(0, SOC_DEV_FUNC); + dev = pcidev_path_on_root(SOC_DEV_FUNC); config = dev->chip_info; /* Set up default verb tables - Just HDMI audio */ diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index 0b07ea8c4c..71aa0a3459 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -312,7 +312,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) static unsigned long acpi_fill_dmar(unsigned long current) { uint32_t vtbar, tmp = current; - struct device *dev = dev_find_slot(0, VTD_DEV_FUNC); + struct device *dev = pcidev_path_on_root(VTD_DEV_FUNC); uint16_t bdf, hpet_bdf[8]; uint8_t i, j; @@ -329,7 +329,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) current += acpi_create_dmar_ds_ioapic(current, 9, 0, 5, 4); /* Get the PCI BDF for the PCH I/O APIC */ - dev = dev_find_slot(0, LPC_DEV_FUNC); + dev = pcidev_path_on_root(LPC_DEV_FUNC); bdf = pci_read_config16(dev, 0x6c); current += acpi_create_dmar_ds_ioapic(current, 8, (bdf >> 8), PCI_SLOT(bdf), PCI_FUNC(bdf)); diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c index d5c5f19b4e..88f7376ede 100644 --- a/src/soc/intel/quark/romstage/fsp1_1.c +++ b/src/soc/intel/quark/romstage/fsp1_1.c @@ -84,7 +84,7 @@ void soc_memory_init_params(struct romstage_params *params, size_t rmu_data_len; /* Locate the configuration data from devicetree.cb */ - dev = dev_find_slot(0, LPC_DEV_FUNC); + dev = pcidev_path_on_root(LPC_DEV_FUNC); if (!dev) { printk(BIOS_CRIT, "Error! Device (PCI:0:%02x.%01x) not found, " diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 3e6198805d..23051bde6d 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -120,7 +120,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) die("Microcode file (rmu.bin) not found."); /* Locate the configuration data from devicetree.cb */ - dev = dev_find_slot(0, LPC_DEV_FUNC); + dev = pcidev_path_on_root(LPC_DEV_FUNC); if (!dev) die("ERROR - LPC device not found!"); config = dev->chip_info; -- cgit v1.2.3