From e65affa2ed5d4fea584532c5cf27bf51ed1f56eb Mon Sep 17 00:00:00 2001
From: Robbie Zhang <robbie.zhang@intel.com>
Date: Mon, 13 Feb 2017 12:07:53 -0800
Subject: soc/intel/skylake: add PrmrrSize to chip config
Prmrr configuration is supported by Kabylake FSP-M with UPD provided.
It is required as one of the SGX initialization steps in BIOS.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified uncore PRMRR MSRs get programmed to set
size and boot.
Change-Id: I2b3dc7c92487505165ee429bd1a37bd60ceac8f3
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: https://review.coreboot.org/18361
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
src/soc/intel/skylake/chip.h | 8 ++++++++
src/soc/intel/skylake/romstage/romstage_fsp20.c | 1 +
2 files changed, 9 insertions(+)
(limited to 'src/soc')
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 1b699520ac..07cb8b1669 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -376,6 +376,14 @@ struct soc_intel_skylake_config {
/* Enable/Disable VMX feature */
u8 VmxEnable;
+ /*
+ * PRMRR size setting with three options
+ * 0x02000000 - 32MiB
+ * 0x04000000 - 64MiB
+ * 0x08000000 - 128MiB
+ */
+ u32 PrmrrSize;
+
/* Statically clock gate 8254 PIT. */
u8 clock_gate_8254;
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index e478890930..a4bb6849e4 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -139,6 +139,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
m_cfg->RMT = config->Rmt;
m_cfg->DdrFreqLimit = config->DdrFreqLimit;
m_cfg->VmxEnable = config->VmxEnable;
+ m_cfg->PrmrrSize = config->PrmrrSize;
for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
if (config->PcieRpEnable[i])
mask |= (1<<i);
--
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