From e21866781f73dfa468ce5da3db7e86b39e2bb4d8 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Wed, 29 Jul 2020 23:20:52 +0200 Subject: soc/intel/skylake: Enable CIO depending on devicetree configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, CIO gets enabled by the option Cio2Enable, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the CIO controller. All corresponding mainboards were checked if the devicetree configuration matches the Cio2Enable setting, and missing entries were added. Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/44032 Reviewed-by: Arthur Heymans Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/chip.c | 3 ++- src/soc/intel/skylake/chip.h | 3 --- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 80e89f6cce..9239fd24de 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -229,7 +229,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) memcpy(params->SerialIoDevMode, config->SerialIoDevMode, sizeof(params->SerialIoDevMode)); - params->PchCio2Enable = config->Cio2Enable; + dev = pcidev_path_on_root(PCH_DEVFN_CIO); + params->PchCio2Enable = dev && dev->enabled; dev = pcidev_path_on_root(SA_DEVFN_IMGU); params->SaImguEnable = dev && dev->enabled; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 33fe52c2b6..b1cf4dcb9b 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -300,9 +300,6 @@ struct soc_intel_skylake_config { /* Bus voltage level, default is 3.3V */ enum skylake_i2c_voltage i2c_voltage[CONFIG_SOC_INTEL_I2C_DEV_MAX]; - /* Camera */ - u8 Cio2Enable; - /* eMMC and SD */ u8 ScsEmmcHs400Enabled; u8 EmmcHs400DllNeed; -- cgit v1.2.3