From e1ecfc93af4918c2a9a4647cf550cb7ecc2b92d6 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 16 Sep 2015 15:18:04 -0500 Subject: intel: update common and FSP cache-as-ram parameters Instead of just passing bits, tsc_low, tsc_high, and an opaque pointer to chipset context those fields are bundled into a cache_as_ram_params struct. Additionally, a new struct fsp_car_context is created to hold the FSP information. These could be combined as the existing romstage code assumes what the chipset_context values are, but I'm leaving the concept of "common" alone for the time being. While working in that area the ABI between assembly and C code has changed to just pass a single pointer to cache_as_ram_params struct. Lastly, validate the bootloader cache-as-ram region with the Kconfig options. BUG=chrome-os-partner:44676 BRANCH=None TEST=Built and booted glados. Original-Change-Id: Ib2a0e38477ef7c15cff1836836cfb55e5dc8a58e Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/300190 Original-Reviewed-by: Duncan Laurie Original-Reviewed-by: Leroy P Leahy Change-Id: Ic5a0daa4e2fe5eda0c4d2a45d86baf14ff7b2c6c Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11809 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- src/soc/intel/common/raminit.c | 6 ++++-- src/soc/intel/common/romstage.c | 30 ++++++++++++++++++++---------- src/soc/intel/common/romstage.h | 9 +++++++-- 3 files changed, 31 insertions(+), 14 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c index bdb23e2b64..932d5c36e8 100644 --- a/src/soc/intel/common/raminit.c +++ b/src/soc/intel/common/raminit.c @@ -57,6 +57,7 @@ void raminit(struct romstage_params *params) unsigned long int data; EFI_PEI_HOB_POINTERS hob_ptr; #endif + struct fsp_car_context *fsp_car_context; /* * Find and copy the UPD region to the stack so the platform can modify @@ -68,7 +69,8 @@ void raminit(struct romstage_params *params) * region in the FSP binary. */ post_code(0x34); - fsp_header = params->chipset_context; + fsp_car_context = params->chipset_context; + fsp_header = fsp_car_context->fih; vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset + fsp_header->ImageBase); printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr); @@ -167,7 +169,7 @@ void raminit(struct romstage_params *params) } /* Save the FSP runtime parameters. */ - fsp_set_runtime(params->chipset_context, hob_list_ptr); + fsp_set_runtime(fsp_header, hob_list_ptr); /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ cbmem_root = get_next_resource_hob(&bootldr_tolum_guid, hob_list_ptr); diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c index 0d5e85fa67..f4ee250203 100644 --- a/src/soc/intel/common/romstage.c +++ b/src/soc/intel/common/romstage.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -48,22 +49,22 @@ #include /* Entry from cache-as-ram.inc. */ -asmlinkage void *romstage_main(unsigned int bist, - uint32_t tsc_low, uint32_t tsc_high, - void *chipset_context) +asmlinkage void *romstage_main(struct cache_as_ram_params *car_params) { void *top_of_stack; struct pei_data pei_data; + struct fsp_car_context *fsp_car_context; struct romstage_params params = { - .bist = bist, + .bist = car_params->bist, .pei_data = &pei_data, - .chipset_context = chipset_context, + .chipset_context = car_params->chipset_context, }; + fsp_car_context = car_params->chipset_context; post_code(0x30); /* Save timestamp data */ - timestamp_init((((uint64_t)tsc_high) << 32) | (uint64_t)tsc_low); + timestamp_init(car_params->tsc); timestamp_add_now(TS_START_ROMSTAGE); memset(&pei_data, 0, sizeof(pei_data)); @@ -76,9 +77,8 @@ asmlinkage void *romstage_main(unsigned int bist, console_init(); /* Display parameters */ - printk(BIOS_SPEW, "bist: 0x%08x\n", bist); - printk(BIOS_SPEW, "tsc_low: 0x%08x\n", tsc_low); - printk(BIOS_SPEW, "tsc_hi: 0x%08x\n", tsc_high); + printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist); + printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc); printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", CONFIG_MMCONF_BASE_ADDRESS); printk(BIOS_INFO, "Using: %s\n", @@ -88,7 +88,17 @@ asmlinkage void *romstage_main(unsigned int bist, /* Display FSP banner */ printk(BIOS_DEBUG, "FSP TempRamInit successful\n"); - print_fsp_info(params.chipset_context); + print_fsp_info(fsp_car_context->fih); + + if (fsp_car_context->bootloader_car_start != CONFIG_DCACHE_RAM_BASE || + fsp_car_context->bootloader_car_end != + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) { + printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n", + CONFIG_DCACHE_RAM_BASE, + CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE, + (long)fsp_car_context->bootloader_car_start, + (long)fsp_car_context->bootloader_car_end); + } /* Get power state */ params.power_state = fill_power_state(); diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h index b35ff6652a..56ab467085 100644 --- a/src/soc/intel/common/romstage.h +++ b/src/soc/intel/common/romstage.h @@ -29,6 +29,12 @@ #include #include /* chip_power_state */ +struct cache_as_ram_params { + uint64_t tsc; + uint32_t bist; + void *chipset_context; +}; + struct romstage_params { unsigned long bist; struct chipset_power_state *power_state; @@ -85,8 +91,7 @@ void report_memory_config(void); void report_platform_info(void); asmlinkage void romstage_after_car(void *chipset_context); void romstage_common(struct romstage_params *params); -asmlinkage void *romstage_main(unsigned int bist, uint32_t tsc_lo, - uint32_t tsc_high, void *chipset_context); +asmlinkage void *romstage_main(struct cache_as_ram_params *car_params); void *setup_stack_and_mtrrs(void); void set_max_freq(void); void soc_after_ram_init(struct romstage_params *params); -- cgit v1.2.3