From e186821952ad7e2248d63ba21041fe84f756816e Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 28 Jul 2021 11:30:59 -0600 Subject: soc/intel/tigerlake: Clear RTC_BATTERY_DEAD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS and backed up to flash (RW_NVRAM). However, on the very first boot after a flash of the full SPI image (so RW_NVRAM is empty), if RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before FSP-M finishes (which appears to be the current location that RTC_BATTERY_DEAD is cleared on this platform). This is because vbnv_cmos_failed() will still return 1. Therefore, immediately after reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot loop when trying to set the recovery mode bit. Note that this was the behavior for previous generations of Intel PMC programming as well (see southbridge/intel, soc/skylake, soc/broadwell, etc). BUG=b:181678769 Change-Id: Ie86822f22aa5899a7e446398370424ca5a4ca43d Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/56669 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner --- src/soc/intel/tigerlake/pmutil.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index c980a2cbbd..aee2b3b908 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -184,6 +184,22 @@ static int rtc_failed(uint32_t gen_pmcon_b) return !!(gen_pmcon_b & RTC_BATTERY_DEAD); } +static void clear_rtc_failed(void) +{ + clrbits8(pmc_mmio_regs() + GEN_PMCON_B, RTC_BATTERY_DEAD); +} + +static int check_rtc_failed(uint32_t gen_pmcon_b) +{ + const int failed = rtc_failed(gen_pmcon_b); + if (failed) { + clear_rtc_failed(); + printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", failed); + } + + return failed; +} + int soc_get_rtc_failed(void) { const struct chipset_power_state *ps; @@ -191,12 +207,12 @@ int soc_get_rtc_failed(void) if (acpi_pm_state_for_rtc(&ps) < 0) return 1; - return rtc_failed(ps->gen_pmcon_b); + return check_rtc_failed(ps->gen_pmcon_b); } int vbnv_cmos_failed(void) { - return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B)); + return check_rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B)); } static inline int deep_s3_enabled(void) -- cgit v1.2.3