From dffa8d05e3694df9cce1ad1b201ea02528038695 Mon Sep 17 00:00:00 2001 From: Krishna Prasad Bhat Date: Thu, 28 Mar 2019 21:51:58 +0530 Subject: soc/intel/cannonlake: Add FSP UPD to unlock GPIO pads in devicetree FSP has a UPD to unlock all GPIO pads. This parameter is disabled by default. Add a chip parameter so that GPIO pads can be unlocked on mainboard level in devicetree and therefore this feature can be used if needed. BUG=b:128686027 Change-Id: Iad9e8a209dc3f8ca0c994e8c1da329918409a1d4 Signed-off-by: Krishna Prasad Bhat Reviewed-on: https://review.coreboot.org/c/coreboot/+/32110 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/chip.h | 3 +++ src/soc/intel/cannonlake/fsp_params.c | 3 +++ 2 files changed, 6 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index a81a7c1211..7461d78279 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -407,6 +407,9 @@ struct soc_intel_cannonlake_config { uint8_t DdiPortCDdc; uint8_t DdiPortDDdc; uint8_t DdiPortFDdc; + + /* Unlock all GPIO Pads */ + uint8_t PchUnlockGpioPads; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 25ee5e1ebe..2688557d9b 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -340,6 +340,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Set TccActivationOffset */ tconfig->TccActivationOffset = config->tcc_offset; + + /* Unlock all GPIO pads */ + tconfig->PchUnlockGpioPads = config->PchUnlockGpioPads; } /* Mainboard GPIO Configuration */ -- cgit v1.2.3