From de19bc372b57aaf003dcbbd1dcd55fa1a183ef6e Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Thu, 28 Jul 2022 21:05:10 +0100 Subject: soc/intel/apollolake/acpi: Add bits of TOLUD register The values in this patch were found in the following datasheets: * 334819 (APL) * 336561 (GLK) Signed-off-by: Sean Rhodes Change-Id: I9a4a05f9c764eecaac3d473ba612dca6cc81518f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66234 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Matt DeVillier --- src/soc/intel/apollolake/acpi/northbridge.asl | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 0bea341845..aa45f45fa9 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -19,8 +19,10 @@ Device (MCHC) Offset(0xB4), BGSM, 32, /* Base of Graphics Stolen Memory */ - Offset(0xBC), - TLUD, 32, /* Top of Low Usable DRAM */ + + Offset (0xbc), /* TOLUD (0:0:0:bc) */ + , 20, + TLUD, 12, /* Top of Lower Usable DRAM */ } } @@ -83,7 +85,7 @@ Method (_CRS, 0, Serialized) CreateDwordField (MCRS, PM01._LEN, PLEN) /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ - PMIN = \_SB.PCI0.MCHC.TLUD & 0xFFF00000 + PMIN = ^MCHC.TLUD << 20 /* Use PCR base to ensure PMAX below GPIO controllers attached to _SB */ PMAX = CONFIG_PCR_BASE_ADDRESS & 0xF0000000 @@ -99,7 +101,7 @@ Method (_CRS, 0, Serialized) GMIN = \_SB.PCI0.MCHC.BGSM & 0xFFF00000 /* Read TOLUD */ - GMAX = \_SB.PCI0.MCHC.TLUD & 0xFFF00000 + GMAX = ^MCHC.TLUD << 20 GMAX-- GLEN = GMAX - GMIN + 1 -- cgit v1.2.3