From dcd8114359c6c3033bf8268e800a053a0020ef29 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Tue, 2 Nov 2021 11:51:48 -0600 Subject: soc/amd/cezanne: Enable CBFS_PRELOAD The follow up CLs will use CBFS_PRELOAD. The default CBFS_CACHE_SIZE was derived by examining the `cbfstool print` output and summing the files we intend to preload. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel Change-Id: I208067e6ceec6ffb602a87bee3bf99a0a75c822d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58961 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/cezanne/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc') diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index a09e9f9b8b..dbafa8c11d 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -195,6 +195,7 @@ config ASYNC_FILE_LOADING bool "Loads files from SPI asynchronously" select COOP_MULTITASKING select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + select CBFS_PRELOAD select PAYLOAD_PRELOAD help When enabled, the platform will use the LPC SPI DMA controller to @@ -202,6 +203,10 @@ config ASYNC_FILE_LOADING boot time because the CPUs can be performing useful work while the SPI contents are being preloaded. +config CBFS_CACHE_SIZE + hex + default 0x40000 if CBFS_PRELOAD + config RAMBASE hex default 0x10000000 -- cgit v1.2.3