From d94cff6ab26d482554309041a9317cc3bf5e4b02 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Thu, 16 Mar 2017 17:49:42 -0700 Subject: soc/intel/braswell: Fix most of the issues detected by checkpatch Fix the following errors and warnings detected by checkpatch.pl: ERROR: that open brace { should be on the previous line ERROR: return is not a function, parentheses are not required WARNING: braces {} are not necessary for any arm of this statement WARNING: line over 80 characters WARNING: braces {} are not necessary for single statement blocks WARNING: Avoid unnecessary line continuations WARNING: break is not useful after a goto or return WARNING: else is not generally useful after a break or return False positives are generated by checkpatch for the following test: ERROR: Macros with complex values should be enclosed in parentheses TEST=Build for cyan Change-Id: I19048895145b138a63100b29f829ff446ff71b58 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/18871 Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/soc/intel/braswell/acpi.c | 6 ++-- src/soc/intel/braswell/chip.h | 2 +- src/soc/intel/braswell/cpu.c | 3 +- src/soc/intel/braswell/lpe.c | 4 +-- src/soc/intel/braswell/southcluster.c | 1 - src/soc/intel/braswell/spi.c | 68 +++++++++++++++++------------------ src/soc/intel/braswell/tsc_freq.c | 7 ++-- src/soc/intel/braswell/xhci.c | 3 +- 8 files changed, 45 insertions(+), 49 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 163d7a9eea..0acb90ce7b 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -525,12 +525,10 @@ void southcluster_inject_dsdt(device_t device) if (gnvs) { acpi_create_gnvs(gnvs); /* Fill in the Wifi Region id */ - if (IS_ENABLED(CONFIG_HAVE_REGULATORY_DOMAIN)) { + if (IS_ENABLED(CONFIG_HAVE_REGULATORY_DOMAIN)) gnvs->cid1 = wifi_regulatory_domain(); - } else { - + else gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN; - } acpi_save_gnvs((unsigned long)gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index fc57a6a95d..8c3f143b46 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -58,7 +58,7 @@ struct soc_intel_braswell_config { int disable_slp_x_stretch_sus_fail; /* LPE Audio Clock configuration. */ - enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz. */ + enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz */ /* Native SD Card controller - override controller capabilities. */ uint32_t sdcard_cap_low; diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index aae553cbc9..96c823a537 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -229,7 +229,6 @@ void soc_init_cpus(device_t dev) printk(BIOS_SPEW, "%s/%s ( %s )\n", __FILE__, __func__, dev_name(dev)); - if (mp_init_with_smm(cpu_bus, &mp_ops)) { + if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); - } } diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 40bda1252c..58b5a8d77f 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -142,9 +142,9 @@ static void lpe_stash_firmware_info(device_t dev) /* Also put the address in MMIO space like on C0 BTM */ mmio = find_resource(dev, PCI_BASE_ADDRESS_0); - write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), \ + write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), res->base); - write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), \ + write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), res->size); } diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 4e4d157714..1c450e98b0 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -390,7 +390,6 @@ static int place_device_in_d3hot(device_t dev) DEV_CASE(TXE) : /* TXE cannot be placed in D3Hot. */ return 0; - break; DEV_CASE(PCIE_PORT1) : DEV_CASE(PCIE_PORT2) : DEV_CASE(PCIE_PORT3) : diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index 514e70e418..5121be016b 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -350,43 +350,43 @@ static int spi_setup_opcode(spi_transaction *trans) optypes = (optypes & 0xfffc) | (trans->type & 0x3); writew_(optypes, cntlr.optype); return 0; - } else { - /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; - - /* Write Enable is handled as atomic prefix */ - if (trans->opcode == SPI_OPCODE_WREN) - return 0; - - read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr.menubytes; - opcode_index++) { - if (opmenu[opcode_index] == trans->opcode) - break; - } + } - if (opcode_index == cntlr.menubytes) { - printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", - trans->opcode); - return -1; - } + /* The lock is on. See if what we need is on the menu. */ + uint8_t optype; + uint16_t opcode_index; - optypes = readw_(cntlr.optype); - optype = (optypes >> (opcode_index * 2)) & 0x3; - if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && - optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && - trans->bytesout >= 3) { - /* We guessed wrong earlier. Fix it up. */ - trans->type = optype; - } - if (optype != trans->type) { - printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", - optype); - return -1; - } - return opcode_index; + /* Write Enable is handled as atomic prefix */ + if (trans->opcode == SPI_OPCODE_WREN) + return 0; + + read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); + for (opcode_index = 0; opcode_index < cntlr.menubytes; + opcode_index++) { + if (opmenu[opcode_index] == trans->opcode) + break; + } + + if (opcode_index == cntlr.menubytes) { + printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", + trans->opcode); + return -1; + } + + optypes = readw_(cntlr.optype); + optype = (optypes >> (opcode_index * 2)) & 0x3; + if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && + optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && + trans->bytesout >= 3) { + /* We guessed wrong earlier. Fix it up. */ + trans->type = optype; + } + if (optype != trans->type) { + printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", + optype); + return -1; } + return opcode_index; } static int spi_setup_offset(spi_transaction *trans) diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index 929b6b59bc..b05a007c66 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -41,10 +41,9 @@ static const unsigned int cpu_bus_clk_freq_table[] = { unsigned int cpu_bus_freq_khz(void) { msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL); - if ((clk_info.lo & 0xF) < (sizeof(cpu_bus_clk_freq_table)/sizeof(unsigned int))) - { - return(cpu_bus_clk_freq_table[clk_info.lo & 0xF]); - } + if ((clk_info.lo & 0xF) + < (sizeof(cpu_bus_clk_freq_table) / sizeof(unsigned int))) + return cpu_bus_clk_freq_table[clk_info.lo & 0xF]; return 0; } diff --git a/src/soc/intel/braswell/xhci.c b/src/soc/intel/braswell/xhci.c index e3e3462fa5..76319c0689 100644 --- a/src/soc/intel/braswell/xhci.c +++ b/src/soc/intel/braswell/xhci.c @@ -42,7 +42,8 @@ static void xhci_init(device_t dev) config->usb_comp_bg), REG_SCRIPT_END }; - printk(BIOS_INFO, "Override USB2_COMPBG to: 0x%X\n", config->usb_comp_bg); + printk(BIOS_INFO, "Override USB2_COMPBG to: 0x%X\n", + config->usb_comp_bg); reg_script_run(ops); } } -- cgit v1.2.3