From d801b1feb8a72adaa8d06d8b4d0b63c6e0ff7350 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Fri, 27 Dec 2019 13:28:01 -0800 Subject: soc/intel/tigerlake: Update fsp_params for TGL Add initial fsp upd settings for TGL, both romstage and ramstage upd's to support basic build and boot of TGL RVP. - Add Silicon upd settings which includes * Serial IO/UART settings * Graphics settings * USB2/USB3 settings - Add Romstage upd settings which includes * Pcie Root port settings * IGD initialization * Hyper Threading settings * SMBus controller settings * Debug probe settings BUG=none BRANCH=none TEST=Build and boot Tigerlake rvp board Signed-off-by: Srinidhi N Kaushik Change-Id: I16df66451fd3a681df1222d283d97dd6bdaff0e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37960 Reviewed-by: Wonkyu Kim Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/fsp_params_tgl.c | 94 ++++++++++++++++++++++- src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 90 +++++++++++++++++++++- 2 files changed, 182 insertions(+), 2 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 6fb2f9f597..fe59ac1d42 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -13,9 +13,37 @@ * GNU General Public License for more details. */ +#include +#include +#include #include +#include #include +#include +#include +#include +#include #include +#include +#include + +static void parse_devicetree(FSP_S_CONFIG *params) +{ + const struct soc_intel_tigerlake_config *config; + config = config_of_soc(); + + for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) + params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; + + for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { + params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; + params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; + params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; + } + + for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) + params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; +} static const pci_devfn_t serial_io_dev[] = { PCH_DEVFN_I2C0, @@ -27,6 +55,7 @@ static const pci_devfn_t serial_io_dev[] = { PCH_DEVFN_GSPI0, PCH_DEVFN_GSPI1, PCH_DEVFN_GSPI2, + PCH_DEVFN_GSPI3, PCH_DEVFN_UART0, PCH_DEVFN_UART1, PCH_DEVFN_UART2 @@ -35,7 +64,70 @@ static const pci_devfn_t serial_io_dev[] = { /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { - /* TODO: Update with UPD override as FSP matures */ + int i; + FSP_S_CONFIG *params = &supd->FspsConfig; + + struct device *dev; + struct soc_intel_tigerlake_config *config; + config = config_of_soc(); + + /* Parse device tree and enable/disable Serial I/O devices */ + parse_devicetree(params); + + /* Load VBT before devicetree-specific config. */ + params->GraphicsConfigPtr = (uintptr_t)vbt_get(); + + params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + + dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) + params->PeiGraphicsPeimInit = 1; + else + params->PeiGraphicsPeimInit = 0; + + for (i = 0; i < 8; i++) + params->IomTypeCPortPadCfg[i] = 0x09000000; + + /* USB */ + for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + params->PortUsb20Enable[i] = config->usb2_ports[i].enable; + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; + params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; + params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; + params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + } + + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + params->PortUsb30Enable[i] = config->usb3_ports[i].enable; + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].tx_de_emp) { + params->Usb3HsioTxDeEmphEnable[i] = 1; + params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; + } + if (config->usb3_ports[i].tx_downscale_amp) { + params->Usb3HsioTxDownscaleAmpEnable[i] = 1; + params->Usb3HsioTxDownscaleAmp[i] = + config->usb3_ports[i].tx_downscale_amp; + } + } + + /* Enable xDCI controller if enabled in devicetree and allowed */ + dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1); + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; + + /* PCH UART selection for FSP Debug */ + params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + + mainboard_silicon_init_params(params); +} + +/* Mainboard GPIO Configuration */ +__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } /* Return list of SOC LPSS controllers */ diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 810cff4a20..388ac42649 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -13,10 +13,98 @@ * GNU General Public License for more details. */ +#include +#include #include +#include +#include +#include #include +#include +#include + +/* Debug interface flag */ +enum debug_interface_flag { + DEBUG_INTERFACE_RAM = 0x1, + DEBUG_INTERFACE_UART = 0x2, + DEBUG_INTERFACE_USB3 = 0x4, + DEBUG_INTERFACE_SERIAL_IO = 0x8, + DEBUG_INTERFACE_TRACEHUB = 0x10 +}; + +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_tigerlake_config *config) +{ + unsigned int i; + uint32_t mask = 0; + + /* Set IGD stolen size to 60MB. */ + m_cfg->IgdDvmt50PreAlloc = 0xFE; + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->SaGv = config->SaGv; + m_cfg->UserBd = BOARD_TYPE_ULT_ULX; + m_cfg->RMT = config->RMT; + + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1 << i); + } + m_cfg->PcieRpEnableMask = mask; + + memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, + sizeof(config->PcieClkSrcUsage)); + + for (i = 0; i < CONFIG_MAX_PCIE_CLOCKS; i++) { + if (config->PcieClkSrcUsage[i] == 0) + m_cfg->PcieClkSrcUsage[i] = 0xff; + } + + m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->EnableC6Dram = config->enable_c6dram; + /* Disable BIOS Guard */ + m_cfg->BiosGuard = 0; + + /* UART Debug Log*/ + m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? + DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB; + m_cfg->PcdIsaSerialUartBase = 0x0; + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + + /* + * Skip IGD initialization in FSP if device + * is disable in devicetree.cb. + */ + const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (!dev || !dev->enabled) + m_cfg->InternalGfx = 0; + else + m_cfg->InternalGfx = 0x1; + + /* Enable Hyper Threading */ + m_cfg->HyperThreading = 1; + /* Disable Lock PCU Thermal Management registers */ + m_cfg->LockPTMregs = 0; + /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */ + m_cfg->ChHashMask = 0x30CC; + /* Enable SMBus controller based on config */ + m_cfg->SmbusEnable = config->SmbusEnable; + /* Set debug probe type */ + m_cfg->PlatformDebugConsent = config->DebugConsent; +} void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - /* TODO: Update with UPD override as FSP matures */ + const struct soc_intel_tigerlake_config *config; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + config = config_of_soc(); + + soc_memory_init_params(m_cfg, config); + mainboard_memory_init_params(mupd); +} + +__weak void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } -- cgit v1.2.3