From d6eb72c87eb569000df62456c187329ee4967dc1 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 12 Jan 2021 15:09:57 +0100 Subject: build system: Structure and serialize INTERMEDIATE Target added to INTERMEDIATE all operate on coreboot.pre, each modifying the file in some way. When running them in parallel, coreboot.pre can be read from and written to in parallel which can corrupt the result. Add a function to create those rules that also adds existing INTERMEDIATE targets to enforce an order (as established by evaluation order of Makefile.inc files). While at it, also add the addition to the PHONY target so we don't forget it. BUG=chromium:1154313, b:174585424 TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2 timeout and sercon) and saw that they were executed. Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/Makefile.inc | 4 +--- src/soc/intel/common/block/fast_spi/Makefile.inc | 5 +---- 2 files changed, 2 insertions(+), 7 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 6f9a3051a1..a1771e8582 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -160,8 +160,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ --output $@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -PHONY+=add_amdfw -INTERMEDIATE+=add_amdfw # Calculate firmware position inside the ROM STONEYRIDGE_FWM_ROM_POSITION=$(call int-add, \ @@ -169,7 +167,7 @@ STONEYRIDGE_FWM_ROM_POSITION=$(call int-add, \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000) -add_amdfw: $(obj)/coreboot.pre $(obj)/amdfw.rom +$(call add_intermediate, add_amdfw, $(obj)/coreboot.pre $(obj)/amdfw.rom) printf " DD Adding AMD Firmware at ROM offset 0x%x\n" \ "$(STONEYRIDGE_FWM_ROM_POSITION)" flock $< dd if=$(obj)/amdfw.rom \ diff --git a/src/soc/intel/common/block/fast_spi/Makefile.inc b/src/soc/intel/common/block/fast_spi/Makefile.inc index d99c44fe0c..2ee64eb0d6 100644 --- a/src/soc/intel/common/block/fast_spi/Makefile.inc +++ b/src/soc/intel/common/block/fast_spi/Makefile.inc @@ -35,7 +35,7 @@ smm-y += mmap_boot.c # Check to ensure that no sections in the FMAP cross 16MiB boundary if # the platform supports split decode windows for BIOS region greater # than 16MiB. -check-fmap-16mib-crossing: $(obj)/fmap_config.h +$(call add_intermediate, check-fmap-16mib-crossing, $(obj)/fmap_config.h) flash_offset=$$(printf "%d" $$(cat $(obj)/fmap_config.h | grep "FMAP_SECTION_FLASH_START" | awk '{print $$NF}')); \ for x in $$(cat $(obj)/fmap_config.h | grep "FMAP_TERMINAL_SECTIONS" | cut -d\" -f2); do \ start=$$(printf "%d" $$(cat $(obj)/fmap_config.h | grep "FMAP_SECTION_"$$x"_START" | awk '{print $$NF}')); \ @@ -46,9 +46,6 @@ check-fmap-16mib-crossing: $(obj)/fmap_config.h done; \ if [ $$fail -eq 1 ]; then false; fi -PHONY+=check-fmap-16mib-crossing -INTERMEDIATE+=check-fmap-16mib-crossing - CBFSTOOL_ADD_CMD_OPTIONS += --ext-win-base $(CONFIG_EXT_BIOS_WIN_BASE) --ext-win-size $(CONFIG_EXT_BIOS_WIN_SIZE) endif # CONFIG_FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW -- cgit v1.2.3