From d5855ec5326f7696a22e0da776a63cc350c2dd16 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Thu, 15 Oct 2015 17:17:09 -0700 Subject: FSP1_1: Always use common code Always use the common FSP code. Remove the FSP_RAM_INIT, FSP_ROMSTAGE, FSP_STACK and FSP_STAGE_CACHE Kconfig values. BRANCH=none BUG=None TEST=Build and run on Kunimitsu Change-Id: Ib3d015cb2dc257e46c2340cc7bc09cf0ffb0492c Signed-off-by: Patrick Georgi Original-Commit-Id: 5197b1354d138759dfaa428c665de6cbfb8e8911 Original-Change-Id: I3e3c1c9e6f73009a099c1ec3688dbd8c326fc766 Original-Signed-off-by: Lee Leahy Original-Reviewed-on: https://chromium-review.googlesource.com/306142 Original-Commit-Ready: Leroy P Leahy Original-Tested-by: Leroy P Leahy Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/12158 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy --- src/soc/intel/braswell/Kconfig | 4 ---- src/soc/intel/skylake/Kconfig | 4 ---- 2 files changed, 8 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index e6f22755ad..11d946aa27 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -17,10 +17,6 @@ config CPU_SPECIFIC_OPTIONS select COLLECT_TIMESTAMPS select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED - select FSP_RAM_INIT - select FSP_ROMSTAGE - select FSP_STACK - select FSP_STAGE_CACHE select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d63fa70d9a..b67faab923 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -19,10 +19,6 @@ config CPU_SPECIFIC_OPTIONS select COLLECT_TIMESTAMPS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_MICROCODE_IN_CBFS - select FSP_RAM_INIT - select FSP_ROMSTAGE - select FSP_STACK - select FSP_STAGE_CACHE select GENERIC_GPIO_LIB select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_HARD_RESET -- cgit v1.2.3