From d1a0c5770803e45dabecf6094fccb9895ea76d10 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sun, 30 Jul 2017 11:37:14 +0300 Subject: usbdebug: Consolidate EHCI_BAR setup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is assumption of static EHCI_BAR_INDEX, try to clean it up by bringing BAR programming at one spot. Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/20825 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Stefan Reinauer --- src/soc/amd/stoneyridge/enable_usbdebug.c | 4 ---- src/soc/intel/broadwell/usb_debug.c | 8 -------- 2 files changed, 12 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c index 675f4b7870..db1e4cf231 100644 --- a/src/soc/amd/stoneyridge/enable_usbdebug.c +++ b/src/soc/amd/stoneyridge/enable_usbdebug.c @@ -53,8 +53,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) /* Enable all of the USB controllers */ outb(0xEF, PM_INDEX); outb(0x7F, PM_DATA); - - pci_write_config32(dev, EHCI_BAR_INDEX, base); - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY - | PCI_COMMAND_MASTER); } diff --git a/src/soc/intel/broadwell/usb_debug.c b/src/soc/intel/broadwell/usb_debug.c index 683b4cc522..b19462dc3e 100644 --- a/src/soc/intel/broadwell/usb_debug.c +++ b/src/soc/intel/broadwell/usb_debug.c @@ -41,12 +41,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { - if (!dev) - return; - - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, base); - - /* Enable access to the EHCI memory space registers. */ - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); } -- cgit v1.2.3