From c95d6ffa7cd532243210723e43b977aa880a72e8 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 13 Jul 2017 12:51:19 -0600 Subject: soc/amd/stoneyridge: Convert 48Mhz enable to read/write32 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the appropriate read32() and write32() calls. Remove unnecessary cast. Change-Id: Ib5430bdb30844d3508a09ddb77a969c0628f6c7d Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/20791 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Kyösti Mälkki Reviewed-by: Martin Roth Reviewed-by: Paul Menzel --- src/soc/amd/stoneyridge/early_setup.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c index ca3447f6a7..f1539eae52 100644 --- a/src/soc/amd/stoneyridge/early_setup.c +++ b/src/soc/amd/stoneyridge/early_setup.c @@ -224,18 +224,17 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) void hudson_clk_output_48Mhz(void) { - u32 data, *memptr; + u32 ctrl; /* * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so * 48Mhz will be on ball AP13 (FT3b package) */ - memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40); - data = *memptr; + ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40)); /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ - data &= (u32)~(1<<2); - *memptr = data; + ctrl &= ~(1<<2); + write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl); } static uintptr_t hudson_spibase(void) -- cgit v1.2.3