From c6ee58c790dd6f55b0be83c65fd823f88f4cba91 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Tue, 12 Apr 2016 17:00:52 -0700 Subject: soc/intel/apollolake: Add tsc_freq.c to all the stages Change-Id: I3120a52e21cf4ad03bb1d16b5b2b8a5e68aabf3f Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/14339 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 328a5b43a7..3e307f5b86 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -25,6 +25,7 @@ romstage-y += gpio.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += memmap.c romstage-y += mmap_boot.c +romstage-y += tsc_freq.c smm-y += placeholders.c @@ -40,6 +41,7 @@ ramstage-y += mmap_boot.c ramstage-y += uart.c ramstage-y += northbridge.c ramstage-y += spi.c +ramstage-y += tsc_freq.c postcar-y += exit_car.S postcar-y += memmap.c -- cgit v1.2.3