From c641f7ed9f9083f73ddb69676a74d7e205351baa Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 28 Dec 2018 16:54:54 +0200 Subject: cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pass timestamps and BIST to romstage using the same signature as C_ENVIRONMENT_BOOTBLOCK will. Change-Id: Ic90da6b1b5ac3b56c69b593ba447ed8e05c8a4e2 Signed-off-by: Arthur Heymans Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/30492 Tested-by: build bot (Jenkins) --- src/soc/intel/baytrail/include/soc/romstage.h | 3 +-- src/soc/intel/baytrail/romstage/cache_as_ram.inc | 25 ++++++++++++------------ src/soc/intel/baytrail/romstage/romstage.c | 15 ++++++++++---- src/soc/intel/broadwell/include/soc/romstage.h | 3 +-- src/soc/intel/broadwell/romstage/romstage.c | 14 +++++++++---- 5 files changed, 36 insertions(+), 24 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index ac0f03bfdf..b65c6809a9 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -31,8 +31,7 @@ struct romstage_params { void mainboard_romstage_entry(struct romstage_params *params); void romstage_common(struct romstage_params *params); -void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_lo, - uint32_t tsc_high); + void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); void tco_disable(void); diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index 8602237d28..4326636bfd 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -176,23 +176,24 @@ addrsize_set_high: post_code(0x29) /* Setup the stack. */ - movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax - movl %eax, %esp + mov $_car_stack_end, %esp - /* Push the initial TSC value from boot block. The low 32 bits are - * in mm1, and the high 32 bits are in mm2. */ + /* Need to align stack to 16 bytes at call instruction. Account for + the pushes below. */ + andl $0xfffffff0, %esp + subl $4, %esp + + /* push TSC and BIST to stack */ + movd %mm0, %eax + pushl %eax /* BIST */ movd %mm2, %eax - pushl %eax + pushl %eax /* tsc[63:32] */ movd %mm1, %eax - pushl %eax - /* Restore the BIST result. */ - movd %mm0, %eax - pushl %eax + pushl %eax /* tsc[31:0] */ -before_romstage: +before_c_entry: post_code(0x2a) - /* Call romstage.c main function. */ - call romstage_main + call bootblock_c_entry_bist /* Should never see this postcode */ post_code(POST_DEAD_CODE) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index a52d3b1c2d..4b499061e9 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -95,8 +96,7 @@ static void spi_init(void) } /* Entry from cache-as-ram.inc. */ -void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low, - uint32_t tsc_hi) +static void romstage_main(uint64_t tsc, uint32_t bist) { struct romstage_params rp = { .bist = bist, @@ -104,7 +104,7 @@ void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low, }; /* Save initial timestamp from bootblock. */ - timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); + timestamp_init(tsc); /* Save romstage begin */ timestamp_add_now(TS_START_ROMSTAGE); @@ -131,7 +131,14 @@ void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low, platform_enter_postcar(); /* We don't return here */ - return NULL; +} + +/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, + * keeping changes in cache_as_ram.S easy to manage. + */ +asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) +{ + romstage_main(base_timestamp, bist); } static struct chipset_power_state power_state CAR_GLOBAL; diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index 17d711fc25..31184f9a02 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -29,8 +29,7 @@ struct romstage_params { void mainboard_romstage_entry(struct romstage_params *params); void romstage_common(struct romstage_params *params); -asmlinkage void *romstage_main(unsigned long bist, uint32_t tsc_lo, - uint32_t tsc_high); + void raminit(struct pei_data *pei_data); struct chipset_power_state; diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index afc8216677..b89d948eba 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -64,8 +65,7 @@ static void platform_enter_postcar(void) } /* Entry from cache-as-ram.inc. */ -asmlinkage void *romstage_main(unsigned long bist, - uint32_t tsc_low, uint32_t tsc_hi) +static void romstage_main(uint64_t tsc, uint32_t bist) { struct romstage_params rp = { .bist = bist, @@ -75,7 +75,7 @@ asmlinkage void *romstage_main(unsigned long bist, post_code(0x30); /* Save initial timestamp from bootblock. */ - timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); + timestamp_init(tsc); /* Save romstage begin */ timestamp_add_now(TS_START_ROMSTAGE); @@ -106,8 +106,14 @@ asmlinkage void *romstage_main(unsigned long bist, mainboard_romstage_entry(&rp); platform_enter_postcar(); +} - return NULL; +/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, + * keeping changes in cache_as_ram.S easy to manage. + */ +asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) +{ + romstage_main(base_timestamp, bist); } /* Entry from the mainboard. */ -- cgit v1.2.3