From c32df9aa1659f404635bbb7b6421444c4b2e1e47 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 3 Jul 2023 18:52:36 +0200 Subject: soc/amd/common/block/acpi/ivrs: use IOMMU PCI register definitions Use IOMMU_CAP_BASE_[LO,HI] instead of magic values. Signed-off-by: Felix Held Change-Id: I7032d9f032a22649951ef1535f39b918eb8bd539 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76223 Tested-by: build bot (Jenkins) Reviewed-by: Fred Reitberger Reviewed-by: Eric Lai --- src/soc/amd/common/block/acpi/ivrs.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index ae39775482..17356901f6 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -339,8 +340,8 @@ unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) /* BDF :00.2 */ ivhd->device_id = 0x02 | (nb_dev->bus->secondary << 8); ivhd->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); - ivhd->iommu_base_low = pci_read_config32(iommu_dev, 0x44) & 0xffffc000; - ivhd->iommu_base_high = pci_read_config32(iommu_dev, 0x48); + ivhd->iommu_base_low = pci_read_config32(iommu_dev, IOMMU_CAP_BASE_LO) & 0xffffc000; + ivhd->iommu_base_high = pci_read_config32(iommu_dev, IOMMU_CAP_BASE_HI); cap_offset_0 = pci_read_config32(iommu_dev, ivhd->capability_offset); cap_offset_10 = pci_read_config32(iommu_dev, -- cgit v1.2.3