From c303d741637a2190cd501e835ac07819d01bafea Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Sun, 11 Feb 2018 17:20:34 -0800 Subject: soc/intel/common: Add generic PCR asl Access to PCH Private Configuration Space Register can be addressed via SBERG_BAR, the method is generic across several generations of Intel SOC. BUG=None TEST=None Change-Id: Iaf8c386824ee08cb93cb419ce3cdb2d3fe22a026 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/23698 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Reviewed-by: Subrata Banik --- src/soc/intel/common/acpi/pcr.asl | 90 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 src/soc/intel/common/acpi/pcr.asl (limited to 'src/soc') diff --git a/src/soc/intel/common/acpi/pcr.asl b/src/soc/intel/common/acpi/pcr.asl new file mode 100644 index 0000000000..9dc77e2f03 --- /dev/null +++ b/src/soc/intel/common/acpi/pcr.asl @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* + * Calculate PCR register base at specified PID + * Arg0 - PCR Port ID + */ +Method (PCRB, 1, NotSerialized) +{ + Return (Add (CONFIG_PCR_BASE_ADDRESS, + ShiftLeft (Arg0, PCR_PORTID_SHIFT))) +} + +/* + * Read a PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + */ +Method (PCRR, 2, Serialized) +{ + OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + Return (DATA) +} + +/* + * AND a value with PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + * Arg2 - Value to AND + */ +Method (PCRA, 3, Serialized) +{ + OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + And (DATA, Arg2, DATA) + + /* + * After every write one needs to read an innocuous register + * to ensure the writes are completed for certain ports. This is done + * for all ports so that the callers don't need the per-port knowledge + * for each transaction. + */ + PCRR (Arg0, Arg1) +} + +/* + * OR a value with PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + * Arg2 - Value to OR + */ +Method (PCRO, 3, Serialized) +{ + OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + Or (DATA, Arg2, DATA) + + /* + * After every write one needs to read an innocuous register + * to ensure the writes are completed for certain ports. This is done + * for all ports so that the callers don't need the per-port knowledge + * for each transaction. + */ + PCRR (Arg0, Arg1) +} -- cgit v1.2.3