From bc69ae9823e9260bee6f2db557a6d26c683f4ad2 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 31 Oct 2013 10:46:56 -0500 Subject: baytrail: add lpss iosf functions and regs The low power subsystem devices have a lot of their configuration done in the IOSF sideband message space. Add support for these access methods. BUG=chrome-os-partner:23790 BRANCH=None TEST=Built and booted through depthcharge. Change-Id: I0dd52b952a16ef1280c29301164db041ee87f636 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/175440 Reviewed-by: Duncan Laurie Tested-by: Aaron Durbin Commit-Queue: Aaron Durbin Reviewed-on: http://review.coreboot.org/4921 Reviewed-by: Alexandru Gagniuc Tested-by: build bot (Jenkins) --- src/soc/intel/baytrail/baytrail/iosf.h | 29 +++++++++++++++++++++++++++++ src/soc/intel/baytrail/iosf.c | 22 ++++++++++++++++++++++ 2 files changed, 51 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index b234552bd8..9b59fbc99d 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -68,6 +68,8 @@ uint32_t iosf_usbphy_read(int reg); void iosf_usbphy_write(int reg, uint32_t val); uint32_t iosf_ushphy_read(int reg); void iosf_ushphy_write(int reg, uint32_t val); +uint32_t iosf_lpss_read(int reg); +void iosf_lpss_write(int reg, uint32_t val); /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ @@ -81,6 +83,7 @@ void iosf_ushphy_write(int reg, uint32_t val); #define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ #define IOSF_PORT_USBPHY 0x43 /* USB PHY */ #define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ +#define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ #define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ #define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ @@ -103,6 +106,8 @@ void iosf_ushphy_write(int reg, uint32_t val); #define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) #define IOSF_OP_READ_USHPHY 0x06 #define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1) +#define IOSF_OP_READ_LPSS 0x06 +#define IOSF_OP_WRITE_LPSS (IOSF_OP_READ_LPSS | 1) #define IOSF_OP_READ_SATAPHY 0x00 #define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1) #define IOSF_OP_READ_PCIEPHY 0x00 @@ -167,4 +172,28 @@ void iosf_ushphy_write(int reg, uint32_t val); #define PUNIT_PWRGT_STATUS 0x61 #define PUNIT_GPU_EC_VIRUS 0xd2 +/* + * LPSS Registers + */ +#define LPSS_SIO_DMA1_CTL 0x280 +#define LPSS_I2C1_CTL 0x288 +#define LPSS_I2C2_CTL 0x290 +#define LPSS_I2C3_CTL 0x298 +#define LPSS_I2C4_CTL 0x2a0 +#define LPSS_I2C5_CTL 0x2a8 +#define LPSS_I2C6_CTL 0x2b0 +#define LPSS_I2C7_CTL 0x2b8 +#define LPSS_SIO_DMA2_CTL 0x240 +#define LPSS_PWM1_CTL 0x248 +#define LPSS_PWM2_CTL 0x250 +#define LPSS_HSUART1_CTL 0x258 +#define LPSS_HSUART2_CTL 0x260 +#define LPSS_SPI_CTL 0x268 +# define LPSS_CTL_ACPI_INT_EN (1 << 21) +# define LPSS_CTL_PCI_CFG_DIS (1 << 20) +# define LPSS_CTL_SNOOP (1 << 18) +# define LPSS_CTL_NOSNOOP (1 << 19) +# define LPSS_CTL_PM_CAP_PRSNT (1 << 1) + + #endif /* _BAYTRAIL_IOSF_H_ */ diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 7d420cc627..8016446338 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -165,3 +165,25 @@ void iosf_ushphy_write(int reg, uint32_t val) write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); } + +uint32_t iosf_lpss_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_LPSS) | + IOSF_PORT(IOSF_PORT_LPSS) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); + return read_iosf_reg(MDR_REG); +} + +void iosf_lpss_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_LPSS) | + IOSF_PORT(IOSF_PORT_LPSS) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); +} -- cgit v1.2.3