From b9a09786bcc7f98735d23a58a9119cb4a744b923 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sun, 15 Sep 2024 10:50:19 +0000 Subject: Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence" This reverts commit 88a496a9c81ba6447a4c1453a45d09ee79f30309. This workaround is not valid with the latest Intel PRQ silicon, so I'm dropping it now. Additionally, able to boot to ChromeOS without any hang, and I also ran an S0ix cycle without any failures. BUG=b:244082753 TEST=Able to boot google/rex0 to CrOS. Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/84368 Reviewed-by: Jakub Czapiga Tested-by: build bot (Jenkins) --- src/soc/intel/meteorlake/acpi/tcss.asl | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl index dbe76f25ce..24d28f3b63 100644 --- a/src/soc/intel/meteorlake/acpi/tcss.asl +++ b/src/soc/intel/meteorlake/acpi/tcss.asl @@ -602,13 +602,7 @@ Scope (\_SB.PCI0) } /* Request IOM for D3 cold entry sequence. */ - /* - * FIXME: Remove this workaround after resolving b/244082753 - * - * Document #742990: TCCold exit flow may not complete when processor at package - * C0. The implication is that the system may hang. - */ - // TD3C = 1 + TD3C = 1 } PowerResource (D3C, 5, 0) -- cgit v1.2.3